公开(公告)号：US5555517A

公开(公告)日：1996-09-10

申请号：US368479

申请日：1995-01-04

申请人： Sumeet Agrawal ,  Narayan Hegde

发明人： Sumeet Agrawal ,  Narayan Hegde

IPC分类号： G06F7/50 ,  G06F7/505

CPC分类号： G06F7/5055

摘要： A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic gates. Each circuit block receives as input a varying number of data bits of an input operand and a carry signal and thereafter, generates a product signal and real bit sums corresponding to these data bits. The plurality of logic gates are arranged such that each logic gate receives as input the product signal from a first adjacent circuit block and the carry signal and outputs the carry signal for a second adjacent circuit block. The carry signal is active if the product signal and the carry signal are active. Thus, the delay associated with the first adjacent circuit block is bypassed in favor of the delay associated with the logic gate.

摘要翻译： 进位跳过增量器减轻常规纹波携带增量器所经历的传播延迟，而不采用实质上更大的器件数量，包括与多个逻辑门组合操作的多个电路块。 每个电路块作为输入接收输入操作数和进位信号的变化数量的数据位，然后产生与这些数据位对应的乘积信号和实数位和。 多个逻辑门布置成使得每个逻辑门从第一相邻电路块和进位信号输入乘积信号作为输入，并输出第二相邻电路块的进位信号。 如果产品信号和进位信号有效，进位信号有效。 因此，与第一相邻电路块相关联的延迟被旁路以有利于与逻辑门相关联的延迟。

公开(公告)号：US5524263A

公开(公告)日：1996-06-04

申请号：US201560

申请日：1994-02-25

申请人： James S. Griffth ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： James S. Griffth ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/384 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated. The present invention, upon detection of a partial stall, allocates a partial number of instructions within the clock cycle that causes the partial stall and updates a retirement entry pointer to the ROB but does not advance the resource pointers. Upon the clock cycle of the deassertion of the partial stall, the remainder of the instructions are allocated to the resource buffers and the resource pointers are advanced. In the event a full and partial stall are asserted concurrently, the full stall takes priority.

摘要翻译： 一种用于在处理器停顿状态期间处理资源分配的方法和装置。 作为各种失速条件的结果，处理器的指令发出组件被停止（例如，新指令的发出被冻结）。 当分配的缓冲区资源变满时，会发生一个停顿状态（全停止）。 在寄存器重命名期间发生另一个停顿条件（部分停止），并且给定的指令源于比RAT缓冲器中当前包含的寄存器别名表更大的寄存器宽度。 这是部分宽度数据依赖关系，部分停止被断言。 本发明在检测到完全失速后不在时钟周期内分配任何缓冲器条目，导致完全失速并且资源指针不被提前，并且在该时钟周期期间发出的指令未被分配。 在完全失速消除的时钟周期内，分配资源缓冲区并更新资源分配指针。 本发明在检测到部分失速后，在时钟周期内分配导致部分停止并将退出条目指针更新到ROB但不推进资源指针的部分指令数。 在部分失速消除的时钟周期之后，剩余的指令被分配给资源缓冲区，资源指针被提前。 在全部和部分失速同时被断言的情况下，完全失速优先。

公开(公告)号：US5584037A

公开(公告)日：1996-12-10

申请号：US571377

申请日：1995-12-13

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度和推测执行的微处理器的应用。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

公开(公告)号：US5584038A

公开(公告)日：1996-12-10

申请号：US633905

申请日：1996-04-17

申请人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

发明人： David B. Papworth ,  Andrew F. Glew ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert P. Colwell ,  Steven J. Griffith ,  Shantanu R. Gupta ,  Narayan Hegde

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F5/14 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch anti speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.

摘要翻译： 分配器为循环缓冲区分配条目。 分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。 除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。 每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。 生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。 响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。 分配器具有用于执行无序调度的推测执行的微处理器的应用程序。 分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。 分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。