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1.发明授权Methods and systems to reduce display artifacts when changing display clock rate 有权改变显示时钟速率时减少显示伪影的方法和系统公开(公告)号：US09070198B2
公开(公告)日：2015-06-30
申请号：US13485205
申请日：2012-05-31
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.
摘要翻译： 公开了用于减少或消除由显示时钟的飞行改变引起的显示伪像的方法，系统和计算机可读介质实施例。 根据本发明的实施例，一种方法包括：改变显示时钟的速率，以及调整由显示时钟计时的显示数据处理流水线，以防止基于显示数据处理流水线的像素输出速率的实质性变化 在变化中
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公开(公告)号：US09348355B2
公开(公告)日：2016-05-24
申请号：US12862298
申请日：2010-08-24
申请人： David I. J. Glen , Collis Quinn Carter , Natan Shtutman , Ngar Sze Nancy Chan , Michael Foxcroft
发明人： David I. J. Glen , Collis Quinn Carter , Natan Shtutman , Ngar Sze Nancy Chan , Michael Foxcroft
摘要： An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.
摘要翻译： 一种装置包括时钟电路和多个显示接口电路。 时钟电路提供公共时钟信号。 显示接口电路各自响应公共时钟信号提供相应的显示链路时钟信号。 其中一个显示链路时钟信号处于与另一个显示链路时钟信号不同的时钟速度。
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3.发明申请Methods and Systems to Reduce Display Artifacts When Changing Display Clock Rate 有权改变显示时钟频率时减少显示人工制品的方法和系统公开(公告)号：US20130083043A1
公开(公告)日：2013-04-04
申请号：US13485205
申请日：2012-05-31
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.
摘要翻译： 公开了用于减少或消除由显示时钟的飞行改变引起的显示伪像的方法，系统和计算机可读介质实施例。 根据本发明的实施例，一种方法包括：改变显示时钟的速率，以及调整由显示时钟计时的显示数据处理流水线，以防止基于显示数据处理流水线的像素输出速率的实质性变化 在变化中
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公开(公告)号：US20110050709A1
公开(公告)日：2011-03-03
申请号：US12862303
申请日：2010-08-24
CPC分类号： G06F3/1431 , G09G5/12 , G09G2300/023 , G09G2370/047
摘要： An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.
摘要翻译： 一种装置包括时钟电路和虚拟像素时钟电路。 时钟电路提供公共时钟信号。 虚拟像素时钟电路响应于公共时钟信号提供多个像素时钟信号。 虚拟像素时钟信号之一处于与多个虚拟像素时钟信号中的另一个不同的时钟速度。
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公开(公告)号：US09760333B2
公开(公告)日：2017-09-12
申请号：US12862303
申请日：2010-08-24
CPC分类号： G06F3/1431 , G09G5/12 , G09G2300/023 , G09G2370/047
摘要： An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.
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公开(公告)号：US20110050314A1
公开(公告)日：2011-03-03
申请号：US12862298
申请日：2010-08-24
申请人： David I.J. Glen , Collis Quinn Carter , Natan Shtutman , Ngar Sze Nancy Chan , Michael Foxcroft
发明人： David I.J. Glen , Collis Quinn Carter , Natan Shtutman , Ngar Sze Nancy Chan , Michael Foxcroft
IPC分类号： G06F1/04
摘要： An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.
摘要翻译： 一种装置包括时钟电路和多个显示接口电路。 时钟电路提供公共时钟信号。 显示接口电路各自响应公共时钟信号提供相应的显示链路时钟信号。 其中一个显示链路时钟信号处于与另一个显示链路时钟信号不同的时钟速度。
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