公开(公告)号：US07084679B2

公开(公告)日：2006-08-01

申请号：US10825191

申请日：2004-04-15

申请人： John Wayne Hartfiel ,  Neil Ambalal Panchal

发明人： John Wayne Hartfiel ,  Neil Ambalal Panchal

IPC分类号： H03L7/00

CPC分类号： G06F1/12

摘要： An apparatus, a method, and a computer program product are provided for producing a synchronous divider reset signal. A notorious concern with multiple non-integer frequency ratio synchronous source clocks has been the time of edge alignment between the respective clocks. To address this concern, a number of latches can be utilized in order to detect alignment of the edges of these clocks. Specifically, the latches are employed to assist in the production of a synchronous divider reset signal for downstream dividers that are utilized in many microprocessors today. Hence, all of the downstream dividers can be properly synchronized to alleviate any errors that can occur between respective macros of a microprocessor chip resulting from misalignment of clock edges.

摘要翻译： 提供了一种用于产生同步分频器复位信号的装置，方法和计算机程序产品。 多个非整数频率比同步源时钟的臭名昭着的关注已经是各个时钟之间的边缘对准的时间。 为了解决这个问题，可以使用多个锁存器来检测这些时钟的边沿对齐。 具体地说，锁存器用于协助生产用于当今许多微处理器中的下游分频器的同步分频器复位信号。 因此，所有下游分频器可以被正确地同步以减轻由于时钟边缘的未对准而导致的微处理器芯片的各个宏之间可能发生的任何错误。