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1.发明授权公开(公告)号：US07266463B2
公开(公告)日：2007-09-04
申请号：US11126120
申请日：2005-05-10
IPC分类号： G01R19/00
CPC分类号： G01R31/3167 , G01R31/31924
摘要： An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.
摘要翻译： 提供了用于识别模拟电气系统中的信号的装置，方法和计算机程序产品。 控制该信号识别电路的定时的ID选择信号包括向上计数并识别相应信号的顺序号码。 要识别的信号位于一组输入/输出（I / O）引脚上。 一个多路复用器（第一）响应于ID选择信号选择一个特定的I / O引脚。 隔离电压源连接到该多路复用器，并将所选择的信号提供给另一个多路复用器（第二）。 响应于ID选择信号，第二多路复用器从该隔离电压源切换到接地电位。 隔离电压源浮动在所选I / O驱动器引脚的直流电平上。 因此，通过连接到所选信号的I / O引脚和第二多路复用器的输出，可以识别所选择的信号，然后探测。
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公开(公告)号：US20090210566A1
公开(公告)日：2009-08-20
申请号：US12032990
申请日：2008-02-18
IPC分类号： G06F3/00
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译： 本发明提供一种系统。 该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号 通过输出引脚基于自识别控制信号。 每个输出引脚耦合到外部系统。 处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。
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公开(公告)号：US5967796A
公开(公告)日：1999-10-19
申请号：US27794
申请日：1998-02-23
CPC分类号： H01R31/02 , G06F13/409 , H01R12/721 , H01R2201/06 , H01R2201/20
摘要： An interface cable which allows access to an operational Peripheral Component Interconnect (PCI) bus compatible circuit board is disclosed. A flat flexible cable (30,72) secures a plurality of connectors (50,32,36,38) at substantially equal intervals. The connectors on the flat cable are adapted to receive a connection (62,63,64,66,68) on a first edge of the PCI compatible circuit board (82,90). When the PCI compatible circuit board is plugged into the flat flexible cable, a second edge of the PCI compatible circuit board which is opposite the first edge is free to move laterally, away from neighboring circuit boards in response to a flexing of the flat flexible cable. Open space is created adjacent to the PCI compatible circuit board allowing sufficient access to surfaces of the functioning PCI compatible circuit board for testing purpose.
摘要翻译： 公开了允许访问操作的外围组件互连（PCI）总线兼容电路板的接口电缆。 扁平柔性电缆（30,72）以大致相等的间隔固定多个连接器（50,32,36,38）。 扁平电缆上的连接器适于在PCI兼容电路板（82,90）的第一边缘上接收连接（62,66,66,66,68）。 当PCI兼容电路板插入扁平柔性电缆时，与第一边缘相对的PCI兼容电路板的第二边缘可自由地横向移动，以响应于扁平柔性电缆的弯曲而远离相邻电路板 。 创建与PCI兼容电路板相邻的开放空间，允许充分访问运行中的PCI兼容电路板的表面进行测试。
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4.发明授权Method and apparatus for ensuring synchronization of clocks in a multiple clock system 失效确保多时钟系统中时钟同步的方法和装置公开(公告)号：US07084679B2
公开(公告)日：2006-08-01
申请号：US10825191
申请日：2004-04-15
IPC分类号： H03L7/00
CPC分类号： G06F1/12
摘要： An apparatus, a method, and a computer program product are provided for producing a synchronous divider reset signal. A notorious concern with multiple non-integer frequency ratio synchronous source clocks has been the time of edge alignment between the respective clocks. To address this concern, a number of latches can be utilized in order to detect alignment of the edges of these clocks. Specifically, the latches are employed to assist in the production of a synchronous divider reset signal for downstream dividers that are utilized in many microprocessors today. Hence, all of the downstream dividers can be properly synchronized to alleviate any errors that can occur between respective macros of a microprocessor chip resulting from misalignment of clock edges.
摘要翻译： 提供了一种用于产生同步分频器复位信号的装置，方法和计算机程序产品。 多个非整数频率比同步源时钟的臭名昭着的关注已经是各个时钟之间的边缘对准的时间。 为了解决这个问题，可以使用多个锁存器来检测这些时钟的边沿对齐。 具体地说，锁存器用于协助生产用于当今许多微处理器中的下游分频器的同步分频器复位信号。 因此，所有下游分频器可以被正确地同步以减轻由于时钟边缘的未对准而导致的微处理器芯片的各个宏之间可能发生的任何错误。
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5.发明授权Multi-chip digital system having a plurality of controllers with self-identifying signal 失效具有多个具有自识别信号的控制器的多芯片数字系统公开(公告)号：US08020058B2
公开(公告)日：2011-09-13
申请号：US12032990
申请日：2008-02-18
IPC分类号： G01R31/28
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译： 本发明提供一种系统。 该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号 通过输出引脚基于自识别控制信号。 每个输出引脚耦合到外部系统。 处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。
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6.发明授权Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted 失效具有多个具有输入和输出引脚的控制器的多芯片数字系统，其中接收和发送自识别信号公开(公告)号：US07409469B2
公开(公告)日：2008-08-05
申请号：US10870459
申请日：2004-06-17
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.
摘要翻译： 本发明提供一种包括控制器和处理器的系统。 所述控制器至少包括输出引脚和多个输入引脚，并且被配置为通过所述多个输入引脚中的一个或多个接收自识别控制信号，并且基于所述输出引脚基于所述输出引脚传输控制器自识别信号 自我识别控制信号。 处理器耦合到控制器并被配置为产生自识别控制信号并将自识别控制信号发送到控制器。
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