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公开(公告)号：US20060221658A1
公开(公告)日：2006-10-05
申请号：US11422529
申请日：2006-06-06
IPC分类号： G11C15/00
CPC分类号： G06F21/554 , G06F7/02 , G06F21/567 , G06F2207/025 , G11C15/00 , H04L63/0227 , H04L63/12 , H04L63/1441
摘要： A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.
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2.发明申请APPARATUS AND METHOD FOR MEMORY EFFICIENT, PROGRAMMABLE, PATTERN MATCHING FINITE STATE MACHINE HARDWARE 失效存储器效率，可编程，图形匹配有限状态机硬件的装置和方法公开(公告)号：US20060120137A1
公开(公告)日：2006-06-08
申请号：US10799367
申请日：2004-03-12
IPC分类号： G11C11/24
CPC分类号： G06F21/554 , G06F7/02 , G06F21/567 , G06F2207/025 , G11C15/00 , H04L63/0227 , H04L63/12 , H04L63/1441
摘要： A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.
摘要翻译： 可编程有限状态机（FSM）部分地包括第一和第二存储器，以及耦合到每个存储器的选择电路。 当接收到表示k位输入符号和m位当前状态的（k + m）位字时，第一存储器提供存储在其中的一个或多个匹配转换规则。 选择电路选择最具体的提供的规则。 过渡规则以一般性的排序顺序存储在第一存储器中。 第二个存储器接收所选择的转移规则并提供FSM的下一个状态。 第一存储器可以是三进制内容可寻址存储器，并且第二存储器可以是静态随机存取存储器。 内容可寻址存储器和静态随机存储器的内容由最小化表示下一状态转换功能所需的术语数量的算法确定。
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3.发明申请Integrated Circuit Apparatus And Method For High Throughput Signature Based Network Applications 审中-公开基于高吞吐量签名的网络应用的集成电路设备及方法公开(公告)号：US20070230445A1
公开(公告)日：2007-10-04
申请号：US11539607
申请日：2006-10-06
IPC分类号： H04L12/66
CPC分类号： H04L65/601 , H04L63/0236 , H04L63/0245
摘要： An architecture for an integrated circuit apparatus and method that allows significant performance improvements for signature based network applications. In various embodiments the architecture allows high throughput classification of packets into network streams, packet reassembly of such streams, filtering and pre-processing of such streams, pattern matching on header and payload content of such streams, and action execution based upon rule-based policy for multiple network applications, simultaneously at wire speed. The present invention is improved over the prior art designs, in performance, flexibility and pattern database size.
摘要翻译： 用于集成电路装置和方法的架构，其允许基于签名的网络应用程序的显着性能改进。 在各种实施例中，架构允许分组进入网络流的高吞吐量分类，这样的流的分组重组，对这些流的过滤和预处理，这些流的报头和有效载荷内容上的模式匹配以及基于规则的策略的动作执行 对于多个网络应用，同时以线速度。 在现有技术设计中，在性能，灵活性和模式数据库大小方面改进了本发明。
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4.发明授权Apparatus and method for generating state transition rules for memory efficient programmable pattern matching finite state machine hardware 有权用于产生存储器有效可编程模式匹配有限状态机硬件的状态转换规则的装置和方法公开(公告)号：US07219319B2
公开(公告)日：2007-05-15
申请号：US11422520
申请日：2006-06-06
IPC分类号： G06F17/50
CPC分类号： H04L63/12
摘要： A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.
摘要翻译： 可编程有限状态机（FSM）部分地包括第一和第二存储器，以及耦合到每个存储器的选择电路。 当接收到表示k位输入符号和m位当前状态的（k + m）位字时，第一存储器提供存储在其中的一个或多个匹配转换规则。 选择电路选择最具体的提供的规则。 过渡规则以一般性的排序顺序存储在第一存储器中。 第二个存储器接收所选择的转移规则并提供FSM的下一个状态。 第一存储器可以是三进制内容可寻址存储器，并且第二存储器可以是静态随机存取存储器。 内容可寻址存储器和静态随机存储器的内容由最小化表示下一状态转换功能所需的术语数量的算法确定。
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5.发明授权Apparatus and method for memory efficient, programmable, pattern matching finite state machine hardware 失效用于存储器高效，可编程，模式匹配的有限状态机硬件的装置和方法公开(公告)号：US07082044B2
公开(公告)日：2006-07-25
申请号：US10799367
申请日：2004-03-12
IPC分类号： G11C13/00
CPC分类号： G06F21/554 , G06F7/02 , G06F21/567 , G06F2207/025 , G11C15/00 , H04L63/0227 , H04L63/12 , H04L63/1441
摘要： A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.
摘要翻译： 可编程有限状态机（FSM）部分地包括第一和第二存储器，以及耦合到每个存储器的选择电路。 当接收到表示k位输入符号和m位当前状态的（k + m）位字时，第一存储器提供存储在其中的一个或多个匹配转换规则。 选择电路选择最具体的提供的规则。 过渡规则以一般性的排序顺序存储在第一存储器中。 第二个存储器接收所选择的转移规则并提供FSM的下一个状态。 第一存储器可以是三进制内容可寻址存储器，并且第二存储器可以是静态随机存取存储器。 内容可寻址存储器和静态随机存储器的内容由最小化表示下一状态转换功能所需的术语数量的算法确定。
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6.发明授权Apparatus and method of ordering state transition rules for memory efficient, programmable, pattern matching finite state machine hardware 失效用于存储器高效，可编程，模式匹配有限状态机硬件的状态转换规则的装置和方法公开(公告)号：US07301792B2
公开(公告)日：2007-11-27
申请号：US11422529
申请日：2006-06-06
IPC分类号： G11C15/00
CPC分类号： G06F21/554 , G06F7/02 , G06F21/567 , G06F2207/025 , G11C15/00 , H04L63/0227 , H04L63/12 , H04L63/1441
摘要： A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.
摘要翻译： 可编程有限状态机（FSM）部分地包括第一和第二存储器，以及耦合到每个存储器的选择电路。 当接收到表示k位输入符号和m位当前状态的（k + m）位字时，第一存储器提供存储在其中的一个或多个匹配转换规则。 选择电路选择最具体的提供的规则。 过渡规则以一般性的排序顺序存储在第一存储器中。 第二个存储器接收所选择的转移规则并提供FSM的下一个状态。 第一存储器可以是三进制内容可寻址存储器，并且第二存储器可以是静态随机存取存储器。 内容可寻址存储器和静态随机存储器的内容由最小化表示下一状态转换功能所需的术语数量的算法确定。
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7.发明申请Integrated Circuit Apparatus And Method for High Throughput Signature Based Network Applications 审中-公开基于高吞吐量签名的网络应用的集成电路设备及方法公开(公告)号：US20070195814A1
公开(公告)日：2007-08-23
申请号：US11539603
申请日：2006-10-06
IPC分类号： H04L12/66
CPC分类号： H04L65/601 , H04L63/0236 , H04L63/0245
摘要： An architecture for an integrated circuit apparatus and method that allows significant performance improvements for signature based network applications. In various embodiments the architecture allows high throughput classification of packets into network streams, packet reassembly of such streams, filtering and pre-processing of such streams, pattern matching on header and payload content of such streams, and action execution based upon rule-based policy for multiple network applications, simultaneously at wire speed. The present invention is improved over the prior art designs, in performance, flexibility and pattern database size.
摘要翻译： 用于集成电路装置和方法的架构，其允许基于签名的网络应用程序的显着性能改进。 在各种实施例中，架构允许分组进入网络流的高吞吐量分类，这样的流的分组重组，对这些流的过滤和预处理，这些流的报头和有效载荷内容上的模式匹配以及基于规则的策略的动作执行 对于多个网络应用，同时以线速度。 在现有技术设计中，在性能，灵活性和模式数据库大小方面改进了本发明。
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8.发明申请Apparatus and Method For Memory Efficient, Programmable, Pattern Matching Finite State Machine Hardware 有权高效，可编程，模式匹配有限状态机硬件的设备和方法公开(公告)号：US20060253816A1
公开(公告)日：2006-11-09
申请号：US11422520
申请日：2006-06-06
IPC分类号： G06F17/50
CPC分类号： H04L63/12
摘要： A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.
摘要翻译： 可编程有限状态机（FSM）部分地包括第一和第二存储器，以及耦合到每个存储器的选择电路。 当接收到表示k位输入符号和m位当前状态的（k + m）位字时，第一存储器提供存储在其中的一个或多个匹配转换规则。 选择电路选择最具体的提供的规则。 过渡规则以一般性的排序顺序存储在第一存储器中。 第二个存储器接收所选择的转移规则并提供FSM的下一个状态。 第一存储器可以是三进制内容可寻址存储器，并且第二存储器可以是静态随机存取存储器。 内容可寻址存储器和静态随机存储器的内容由最小化表示下一状态转换功能所需的术语数量的算法确定。
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