公开(公告)号：US20060150134A1

公开(公告)日：2006-07-06

申请号：US11357964

申请日：2006-02-22

申请人： Noriko Shinomiya

发明人： Noriko Shinomiya

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5063

摘要： In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

公开(公告)号：US5943486A

公开(公告)日：1999-08-24

申请号：US752413

申请日：1996-11-19

申请人： Masahiro Fukui ,  Noriko Shinomiya

发明人： Masahiro Fukui ,  Noriko Shinomiya

IPC分类号： G06F17/50 ,  H01L21/98

CPC分类号： G06F17/5077 ,  G06F17/5081

摘要： Elements such as a transistor having a terminal corresponding to a wire junction are abstracted by using rectangles, and a spit penetrating these rectangles is introduced in a layout area where the rectangles are disposed. On the spit, a wire junction for allocating a wire is provided. The terminals of the rectangles corresponding to the wire junctions and the wire junctions on the spit are set as net targets, and connection information on these net targets is generated. A scan line for scanning the layout area from its left end to its right end and a front for tracing the net targets are introduced. While conducting rightward scanning by the scan line, the front is proceeded from one net target to the other net target. The trace of the front is provided as a wire element.

摘要翻译： 通过使用矩形来抽出具有对应于线结的端子的晶体管的元件，并且在布置有矩形的布局区域中引入穿透这些矩形的吐丝。 在吐痰中，提供用于分配电线的电线接头。 对应于线路连接处的矩形端子和吐丝上的电线接头被设置为净目标，并且生成关于这些网络目标的连接信息。 介绍了用于从左端到右端扫描布局区域的扫描线和用于跟踪网目标的前端。 在扫描线进行向右扫描时，前方从一个净目标进入另一个目标。 前面的痕迹作为线元件提供。

公开(公告)号：US08024689B2

公开(公告)日：2011-09-20

申请号：US11798678

申请日：2007-05-16

申请人： Noriko Shinomiya ,  Kiyohito Mukai

发明人： Noriko Shinomiya ,  Kiyohito Mukai

IPC分类号： G06F17/50 ,  H01L27/118 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit.In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

摘要翻译： 本发明的目的是提供一种易于设计并具有低布线电阻的半导体集成电路，以及用于设计半导体集成电路的方法和装置。 在根据本发明的半导体集成电路装置中，第一布线层设置有多个具有相等宽度的信号布线，该信号布线以规则的间隔彼此平行地布置，并且至少两条信号布线是 彼此相邻地彼此电连接。

公开(公告)号：US20070272949A1

公开(公告)日：2007-11-29

申请号：US11798678

申请日：2007-05-16

申请人： Noriko Shinomiya ,  Kiyohito Mukai

发明人： Noriko Shinomiya ,  Kiyohito Mukai

IPC分类号： H01L27/10

CPC分类号： H01L23/528 ,  G06F17/5077 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

摘要翻译： 本发明的目的是提供一种易于设计并具有低布线电阻的半导体集成电路，以及用于设计半导体集成电路的方法和装置。 在根据本发明的半导体集成电路装置中，第一布线层设置有多个具有相等宽度的信号布线，该信号布线以规则的间隔彼此平行地布置，并且至少两条信号布线是 彼此相邻地彼此电连接。

公开(公告)号：US06336207B1

公开(公告)日：2002-01-01

申请号：US09084019

申请日：1998-05-26

申请人： Noriko Shinomiya ,  Masahiro Fukui

发明人： Noriko Shinomiya ,  Masahiro Fukui

IPC分类号： G06F1750

摘要： Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction reaction a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

公开(公告)号：US06202195B1

公开(公告)日：2001-03-13

申请号：US08898562

申请日：1997-07-22

申请人： Masakazu Tanaka ,  Masahiro Fukui ,  Noriko Shinomiya

发明人： Masakazu Tanaka ,  Masahiro Fukui ,  Noriko Shinomiya

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： In designing a layout for a deep-submicron semiconductor integrated circuit, a violational wire involving a violation of the delay limitation is extracted based on information representing a layout result obtained in a layout step. In order to extend a wire spacing between such an extracted wire and its neighboring wire to above a predetermined wire spacing, the neighboring wire is subjected to parallel displacement. If such a parallel displacement causes a distance of separation between the parallelly-displaced wire and its neighboring component to fall below a predetermined distance of separation, the component in question is shifted in order of extending the separation distance. Accordingly, even if the delay time of wire is dominant in comparison with that of element in regard to the signal propagation delay time, violations of the delay limitation occurring when the signal propagation delay time is less than a predetermined delay time can be canceled by a less number of steps.

摘要翻译： 在设计深亚微米半导体集成电路的布局时，基于在布局步骤中获得的布局结果的信息，提取涉及违反延迟限制的违规线。 为了将这种提取的线材和其相邻的线材之间的线间距延伸到预定的线间隔以上，相邻的线材将被平行移动。 如果这种平行位移导致平行移位的线与其相邻部件之间的间隔距离落在预定的分离距离之下，则所述组件按延伸分隔距离的顺序移动。 因此，即使与信号传播延迟时间相比，导线的延迟时间与元件的延迟时间相比是显着的，所以当信号传播延迟时间小于预定延迟时间时发生的延迟限制的违反可以被 步数减少

公开(公告)号：US07441214B2

公开(公告)日：2008-10-21

申请号：US11357964

申请日：2006-02-22

申请人： Noriko Shinomiya

发明人： Noriko Shinomiya

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5063

摘要： In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a predetermined range, while a logic gate in the circuit block is selected when the amount of noise is out of the predetermined range and a bypass condenser is added to the selected logic gate. Therefore, a bypass condenser having a required capacitance can be added in the vicinity of a noise source in the circuit block, whereby the noise can be reliably restricted to the predetermined range.

摘要翻译： 在LSI设计中，输入门级逻辑电路信息，标准单元库信息和构成LSI芯片的电路块的封装信息，使用输入信息对LSI芯片进行噪声分析，并且当量 的噪声在预定范围内，而当噪声量超出预定范围并且旁路电容器被添加到所选择的逻辑门时，选择电路块中的逻辑门。 因此，可以在电路块中的噪声源附近添加具有所需电容的旁路电容器，从而可以将噪声可靠地限制在预定范围内。

公开(公告)号：US20060038201A1

公开(公告)日：2006-02-23

申请号：US11200060

申请日：2005-08-10

申请人： Noriko Shinomiya ,  Masaomi Toyama ,  Hiroyuki Konishi

发明人： Noriko Shinomiya ,  Masaomi Toyama ,  Hiroyuki Konishi

IPC分类号： H01L27/10

CPC分类号： G06F17/5081

摘要： A layout symmetry constraint checking method and apparatus for efficiently checking a layout symmetry constraint is provided. The layout symmetry constraint is checked by performing a first checking step of checking, for example, a match between shapes of a symmetrical element pair for input layout data, a second checking step of checking whether or not a relative positional relationship between elements is contradictory to the layout symmetry constraint, and a third checking step of checking whether or not a geometric placement of the elements satisfies the layout symmetry constraint. When an error occurs in each of the checking steps, a cause for the error is specified and presented to the designer, thereby achieving efficient layout design.

摘要翻译： 提供了一种用于有效地检查布局对称约束的布局对称约束检查方法和装置。 通过执行第一检查步骤来检查布局对称性约束，例如检查用于输入布局数据的对称元件对的形状之间的匹配，第二检查步骤，用于检查元件之间的相对位置关系是否相矛盾 布局对称性约束，以及检查元素的几何位置是否满足布局对称约束的第三检查步骤。 当在每个检查步骤中发生错误时，指定错误的原因并呈现给设计者，从而实现有效的布局设计。

公开(公告)号：US06560759B2

公开(公告)日：2003-05-06

申请号：US09781233

申请日：2001-02-13

申请人： Noriko Shinomiya

发明人： Noriko Shinomiya

IPC分类号： G06F1750

CPC分类号： H01L27/0248

摘要： In a semiconductor integrated circuit device, at least one I/O cell can be disposed in a desired position within a chip. The semiconductor integrated circuit device includes an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to the center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.

摘要翻译： 在半导体集成电路器件中，至少一个I / O单元可以设置在芯片内的期望位置。 半导体集成电路器件包括与I / O单元分离并且设置在设置在芯片的周边部分中的ESD保护电路区域中的ESD保护电路; 所述I / O单元设置成比所述ESD保护电路区域更靠近所述芯片的中心; 以及用于将I / O单元连接到ESD保护电路的导线。

公开(公告)号：US5852562A

公开(公告)日：1998-12-22

申请号：US571130

申请日：1995-12-12

申请人： Noriko Shinomiya ,  Masahiko Toyonaga ,  Masahiro Fukui ,  Toshiro Akino

发明人： Noriko Shinomiya ,  Masahiko Toyonaga ,  Masahiro Fukui ,  Toshiro Akino

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5068

摘要： To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area. By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.

摘要翻译： 为了减少区域中的电路块，本发明提供一种LSI布局设计方法，其具有用于减少区域中的纯布线区的单元改变处理。 通过输入处理，输入电路设计信息和单元库。 然后，通过单元放置处理来设计布置在多个单元行中的单元的布局。 然后，通过布线区高度估计处理来估计单元行之间所需的布线区的高度。 为了减小除了单元布线区域之外的纯布线区域的面积，通过小区改变处理将每个放置的小区改变为具有相同规格和不同形状或不同终端位置的小区。 单元互连的布局是通过布线处理设计的。 基于由上述处理获得的布局，通过掩模图案制备处理制备并提供掩模图案。