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    Conductive belt, method of producing same, and image-forming apparatus having same
    1.
    发明授权
    Conductive belt, method of producing same, and image-forming apparatus having same 失效
    导电带，其制造方法和具有该导电带的图像形成装置

    公开(公告)号：US07740778B2

    公开(公告)日：2010-06-22

    申请号：US11826014

    申请日：2007-07-11

    申请人： Masakazu Tanaka

    发明人： Masakazu Tanaka

    IPC分类号： G03G5/153

    CPC分类号： G03G15/0131 ,  B82Y30/00 ,  G03G15/162

    摘要： A method of producing a conductive belt composed of a base resin containing polybutylene naphthalate resin at not less than 50 mass % nor more than 100 mass % and 1 to 3 mass % of carbon nano-fibers having a DBP oil absorption amount at not less than 150 ml/100 g. The method includes the steps of forming a conductive master batch by mixing the carbon nano-fibers with resin for use in a master batch containing the polybutylene naphthalate resin; mixing the obtained conductive master batch and resin for blending use containing the polybutylene naphthalate resin and not containing the carbon nano-fibers with each other in an unmelted state by setting a mixing mass ratio of the conductive master batch smaller than that of the resin for blending use; and meltingly molding an obtained mixture by an extrusion molder.

    摘要翻译： 制造导电带的方法，所述导电带由含有聚萘二甲酸丁二醇酯树脂的基础树脂组成，所述基材树脂的含量为不低于50质量％，但不超过100质量％和1至3质量％的DBP吸油量的碳纳米纤维为不小于 150ml / 100g。 该方法包括以下步骤：通过将碳纳米纤维与用于含有聚萘二甲酸丁二醇酯树脂的母料中的树脂混合形成导电母料; 将得到的导电母料和用于混合使用的含有聚萘二甲酸丁二醇酯树脂并且不含有碳纳米纤维的树脂在未熔融状态下混合，通过将导电母料的混合质量比设定为小于混合树脂的混合质量比 使用; 并通过挤出成型机将获得的混合物熔融成型。

    Position-dependent variation amount computation method and circuit analysis method
    4.
    发明申请
    Position-dependent variation amount computation method and circuit analysis method 有权
    位置相关变化量计算方法和电路分析方法

    公开(公告)号：US20070186196A1

    公开(公告)日：2007-08-09

    申请号：US11651021

    申请日：2007-01-09

    申请人： Masakazu Tanaka

    发明人： Masakazu Tanaka

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5036

    摘要： Using layout position information as input, in a position-dependent variation amount calculation step, position-dependent variation amount information which is a variation amount of a characteristic parameter or a shape parameter variable depending on an arrangement position of each element constituting a design target semiconductor integrated circuit is calculated. Thereafter, a simulation is performed using circuit information. In the simulation, a value for the circuit information is corrected according to a position-dependent variation amount of the position-dependent variation amount information, and a result of the simulation is calculated. Accordingly, a simulation for a circuit characteristic using a variation amount depending on an arrangement position of a device and the like can be performed with layout position information for a semiconductor integrated circuit.

    摘要翻译： 使用布局位置信息作为输入，在位置相关变化量计算步骤中，作为构成设计目标半导体的每个元件的布置位置的特征参数或形状参数变量的变化量的位置相关变化量信息 计算集成电路。 此后，使用电路信息进行模拟。 在模拟中，根据位置相关变化量信息的位置相关变化量来校正电路信息的值，并且计算模拟结果。 因此，可以利用用于半导体集成电路的布局位置信息来执行使用根据装置的布置位置等的变化量的电路特性的模拟。

    Conductive belt
    5.
    发明授权
    Conductive belt 有权
    导电带

    公开(公告)号：US07150908B2

    公开(公告)日：2006-12-19

    申请号：US10617711

    申请日：2003-07-14

    申请人： Katsumi Terakawa ,  Shunichi Yabushita ,  Masakazu Tanaka ,  Jun Ochi

    发明人： Katsumi Terakawa ,  Shunichi Yabushita ,  Masakazu Tanaka ,  Jun Ochi

    IPC分类号： B32B27/32 ,  G03G15/00 ,  G03G15/01 ,  G03G15/20

    CPC分类号： B32B27/34 ,  B32B7/02 ,  B32B25/04 ,  B32B27/40 ,  Y10T428/24942 ,  Y10T428/2495

    摘要： A conductive belt having a base layer (3) electroconductive and made of a resin, an intermediate layer (5) ionic-conductive and made of an elastomer, and a surface coating layer (7). The base layer (3) has a tensile modulus of elasticity of not less than 500 Mpa and a volume electric resistance value not less than 106 Ω·cm nor more than 1011 Ω·cm. The intermediate layer (5) has a JIS A hardness less than 70, a thickness not less than 50 μm nor more than 600 μm, and a volume electric resistance value not less than 108 Ω·cm nor more than 1014 Ω·cm.

    摘要翻译： 一种导电带，其具有导电性且由树脂制成的基底层（3），由弹性体制成的离子导电的中间层（5）和表面涂层（7）。 基层（3）的拉伸弹性模量不小于500Mpa，体积电阻值不小于10psg，不大于10 11 > Omega.cm。 中间层（5）的JIS A硬度小于70，厚度不小于50μm，不大于600μm，体积电阻值不小于10Ω·cm，cm 超过10±15cm。

    Delay distribution calculation method, circuit evaluation method and false path extraction method
    6.
    发明授权
    Delay distribution calculation method, circuit evaluation method and false path extraction method 有权
    延迟分布计算方法，电路评估方法和假路径提取方法

    公开(公告)号：US07131082B2

    公开(公告)日：2006-10-31

    申请号：US10739309

    申请日：2003-12-19

    申请人： Shuji Tsukiyama ,  Masakazu Tanaka ,  Masahiro Fukui

    发明人： Shuji Tsukiyama ,  Masakazu Tanaka ,  Masahiro Fukui

    IPC分类号： G06F17/50

    CPC分类号： G05B19/0421 ,  G06F17/50 ,  G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

    摘要： Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

    摘要翻译： 计算集成电路中的延迟分布，同时考虑集成电路中的互连或元件之间的性能的相关性，从而提高估计精度。 输入电路信息，集成电路中的互连或元件的性能分布信息，以及互连或元件之间的性能的相关信息。 选择顶点进行计算，并且基于性能分布信息和相关信息来计算在所选择的顶点处的延迟分布和包括所选择的顶点的部分电路中的延迟分布之间的相关性。

    Ceramic filter and catalyst-loaded ceramic filter
    7.
    发明授权
    Ceramic filter and catalyst-loaded ceramic filter 有权
    陶瓷过滤器和催化剂负载陶瓷过滤器

    公开(公告)号：US07048894B2

    公开(公告)日：2006-05-23

    申请号：US10180033

    申请日：2002-06-27

    申请人： Masakazu Tanaka ,  Tosiharu Kondo ,  Hiromi Sano ,  Mamoru Nishimura

    发明人： Masakazu Tanaka ,  Tosiharu Kondo ,  Hiromi Sano ,  Mamoru Nishimura

    IPC分类号： F01N3/28

    CPC分类号： B01D53/9454 ,  F01N3/0222 ,  F01N3/035 ,  F01N2330/06 ,  Y02T10/22 ,  Y10T428/249953

    摘要： A catalyst-loaded ceramic filter made of a ceramic material capable of directly supporting a catalyst component thereon is capable of providing early activation of the catalyst with a low coefficient of thermal expansion and light weight, without compromising the high porosity of the filter substrate. A catalyst-loaded ceramic filter is made of a ceramic material of which one or more kinds of element among its constituent elements is substituted with an element other than the constituent elements, for example a ceramic material with a part of Si or other elements included in cordierite is substituted with W or Co, as a filter substrate of honeycomb structure having a number of cells separated by porous walls, and supporting a catalyst such as a noble metal directly on the W.

    摘要翻译： 由能够直接支撑其上的催化剂组分的陶瓷材料制成的催化剂负载的陶瓷过滤器能够以低的热膨胀系数和重量轻提供催化剂的早期活化，而不会影响过滤器基材的高孔隙率。 载有催化剂的陶瓷过滤器由其组成元素中的一种或多种元素被除了构成元素之外的元素所取代的陶瓷材料制成，例如具有部分Si或其它元素的陶瓷材料 堇青石被W或Co取代，作为蜂窝结构体的过滤基材，其具有多孔隔离的细胞数，并直接在W上负载催化剂如贵金属。

    Method for design of partial circuit
    8.
    发明授权
    Method for design of partial circuit 失效
    部分电路设计方法

    公开(公告)号：US06553544B2

    公开(公告)日：2003-04-22

    申请号：US09816063

    申请日：2001-03-26

    申请人： Masakazu Tanaka ,  Masahiro Fukui

    发明人： Masakazu Tanaka ,  Masahiro Fukui

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045

    摘要： There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed. The step of external condition estimation can be formed so as to include the technology conversion step which technologically converts the layout for external condition extraction, that is prepared in advance, based on the technology information of an integrated circuit, which is the design objective; the layout extraction step of extracting layout extraction information which is external information influencing the operation of the partial circuit from the layout for external condition extraction that has been technologically converted; and the external condition calculation step of calculating external conditions of the partial circuit from the layout extraction information. In addition, by simply replacing the designed partial circuit with a partial circuit of a circuit for evaluation, the evaluation of the designed partial circuit can be easily carried out.

    摘要翻译： 在什么外部条件下，在设计局部电路时，在实际的集成电路中使用诸如库单元的每个部分电路都不存在用于精确估计的常规方法。 因此，通过在集成电路中使用部分电路的外部条件进行估计，使得部分电路根据外部条件进行设计，可以设计具有外部条件的最佳性能的部分电路。 外部条件估计的步骤可以形成为包括技术转换步骤，其技术上将基于作为设计目标的集成电路的技术信息预先准备的用于外部条件提取的布局转换; 布局提取步骤，从技术转换的外部条件提取的布局中提取作为影响部分电路的操作的外部信息的布局提取信息; 以及外部条件计算步骤，根据布局提取信息计算部分电路的外部条件。 此外，通过简单地用设计的电路部分电路代替设计的部分电路，可以容易地进行设计的部分电路的评估。

    Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method
    9.
    发明授权
    Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method 失效
    用于集成电路的布局设计装置，晶体管尺寸确定装置，电路特性评估方法和晶体管尺寸确定方法

    公开(公告)号：US06393601B1

    公开(公告)日：2002-05-21

    申请号：US09034382

    申请日：1998-03-04

    申请人： Masakazu Tanaka ,  Masahiro Fukui

    发明人： Masakazu Tanaka ,  Masahiro Fukui

    IPC分类号： G06F1750

    CPC分类号： H01L27/0207 ,  G06F17/5068

    摘要： The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section. Thus, a transistor size can be determined while taking the diffusion sharing into consideration. In addition, unlike a conventional method, it is no longer necessary to repeatedly re-determine a transistor size and perform a compaction.

    摘要翻译： 本发明在设计集成电路的布局时实现了具有更高精度和更短时间的晶体管尺寸的优化。 扩散共享估计部基于电路数据来估计集成电路的布局中的扩散共享区域。 电路特性评价部根据由扩散共享估计部估计的扩散共享区域的信息，对集成电路的面积，延迟和功耗等特性进行评价。 晶体管尺寸优化部分为构成集成电路的每个晶体管设置各种尺寸候选，将这些尺寸候选提供给扩散共享估计部分和电路特性评估部分，然后从晶体管尺寸候选中选择最佳晶体管尺寸 根据由电路特性评价部得到的评价结果​​进行设定。 因此，可以在考虑扩散共享的同时确定晶体管尺寸。 此外，与常规方法不同，不再需要重复确定晶体管尺寸并进行压实。

    Circuit optimization system
    10.
    发明授权
    Circuit optimization system 失效
    电路优化系统

    公开(公告)号：US06253351B1

    公开(公告)日：2001-06-26

    申请号：US09273909

    申请日：1999-03-22

    申请人： Masahiro Fukui ,  Masakazu Tanaka

    发明人： Masahiro Fukui ,  Masakazu Tanaka

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： An equivalent circuit converter reads out transistor-level circuit diagram data and equivalency conversion rule data, converts circuit data based on the equivalency conversion rule data, and then feeds back the converted circuit data to the circuit diagram data. An estimate calculator reads out the circuit diagram data, which has been converted by the equivalent circuit converter, and environmental variable data, thereby calculating an estimate representing a degree of optimization. In response to the estimates supplied from the estimate calculator, a circuit optimizer selects partial circuits to be subjected to equivalent circuit conversion during the optimization of the circuit. Then, the circuit optimizer sequentially determines whether or not each of the partial circuits should be converted into an associated equivalent circuit, thereby optimizing the entire circuit.

    摘要翻译： 等效电路转换器读出晶体管级电路图数据和等效转换规则数据，根据等效转换规则数据转换电路数据，然后将转换的电路数据反馈回电路图数据。 估计计算器读出由等效电路转换器转换的电路图数据和环境变量数据，由此计算表示优化度的估计。 响应于从估计计算器提供的估计，电路优化器选择在电路优化期间进行等效电路转换的部分电路。 然后，电路优化器顺序地确定每个部分电路是否应该被转换成相关联的等效电路，从而优化整个电路。