-
公开(公告)号：US20100295617A1
公开(公告)日：2010-11-25
申请号：US12763575
申请日：2010-04-20
IPC分类号： H03F3/45
CPC分类号： H01S5/06213 , G09G3/3283 , G09G2300/0426 , H01S5/0427 , H01S5/183 , H03F3/45085 , H03F3/45511 , H03F2200/456 , H03F2203/45408 , H03F2203/45722 , H03K5/2418 , H05B33/0851
摘要： Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input stage and output stage along with a control loop. Collectively, these components operate together to drive the LED with a low headroom voltage while still achieving high driver performance in terms of edge speed and jitter.
摘要翻译： 这里提供了用于发光二极管（LED）的驱动器。 在该驱动器内，在输入级和输出级中采用了几个差分双极晶体管对以及一个控制回路。 总的来说，这些组件一起工作，驱动LED具有较低的净空电压，同时在边缘速度和抖动方面仍能实现高驱动性能。
-
公开(公告)号：US08125273B2
公开(公告)日：2012-02-28
申请号：US12763575
申请日：2010-04-20
IPC分类号： H03F3/45
CPC分类号： H01S5/06213 , G09G3/3283 , G09G2300/0426 , H01S5/0427 , H01S5/183 , H03F3/45085 , H03F3/45511 , H03F2200/456 , H03F2203/45408 , H03F2203/45722 , H03K5/2418 , H05B33/0851
摘要： Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input stage and output stage along with a control loop. Collectively, these components operate together to drive the LED with a low headroom voltage while still achieving high driver performance in terms of edge speed and jitter.
摘要翻译： 这里提供了用于发光二极管（LED）的驱动器。 在该驱动器内，在输入级和输出级中采用了几个差分双极晶体管对以及一个控制回路。 总的来说，这些组件一起工作，驱动LED具有较低的净空电压，同时在边缘速度和抖动方面仍能实现高驱动性能。
-
3.发明申请公开(公告)号：US20120076176A1
公开(公告)日：2012-03-29
申请号：US13235212
申请日：2011-09-16
IPC分类号： H04B1/707
CPC分类号： H03L7/18
摘要： The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.
摘要翻译： 本发明涉及一种包括多个缓冲器和锁相环的电子设备。 对于每个缓冲器，提供分数分频器，其被耦合以接收来自锁相环的输出并且被配置为将分割的输出信号馈送到相应的缓冲器。 提供扩展频谱时钟（SSC）中的扩频时钟控制逻辑级，其被配置为单独调整每个分数分频器的除法值，以便根据扩频单独和独立地调制每个分数分频器的输出信号 频谱调制方案。
-
公开(公告)号：US08653856B2
公开(公告)日：2014-02-18
申请号：US13234318
申请日：2011-09-16
IPC分类号： H03K19/094 , H03B1/00
CPC分类号： H03K19/018528
摘要： A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.
摘要翻译： 提供缓冲区。 缓冲器包括在第一输出节点串联耦合的第一开关和第二开关，第三开关和第四开关，其在第二输出节点串联耦合，第一电流源和第二电流源。 第一电流源与一侧耦合到第一开关和第三开关，并且另一侧耦合到第一电源电压，第二电流源与一侧耦合到第二开关和第四开关，并且第二侧耦合到 第二电源电压。 第一电流源被配置为在第一操作模式和第二操作中调整输出摆幅。 第二电流源被配置为在第一操作模式中调节输出信号的共模电压电平，并且在第二操作模式中提供最大串联电阻。
-
公开(公告)号：US20120074987A1
公开(公告)日：2012-03-29
申请号：US13234318
申请日：2011-09-16
IPC分类号： H03K3/00
CPC分类号： H03K19/018528
摘要： A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.
摘要翻译： 提供缓冲区。 缓冲器包括在第一输出节点串联耦合的第一开关和第二开关，第三开关和第四开关，其在第二输出节点串联耦合，第一电流源和第二电流源。 第一电流源与一侧耦合到第一开关和第三开关，并且另一侧耦合到第一电源电压，第二电流源与一侧耦合到第二开关和第四开关，并且第二侧耦合到 第二电源电压。 第一电流源被配置为在第一操作模式和第二操作中调整输出摆幅。 第二电流源被配置为在第一操作模式中调节输出信号的共模电压电平，并且在第二操作模式中提供最大串联电阻。
-
6.发明授权公开(公告)号：US08588275B2
公开(公告)日：2013-11-19
申请号：US13235212
申请日：2011-09-16
CPC分类号： H03L7/18
摘要： The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.
摘要翻译： 本发明涉及一种包括多个缓冲器和锁相环的电子设备。 对于每个缓冲器，提供分数分频器，其被耦合以接收来自锁相环的输出并且被配置为将分割的输出信号馈送到相应的缓冲器。 提供扩展频谱时钟（SSC）中的扩频时钟控制逻辑级，其被配置为单独调整每个分数分频器的除法值，以便根据扩频单独和独立地调制每个分数分频器的输出信号 频谱调制方案。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.011 秒)
