公开(公告)号：US07782932B2

公开(公告)日：2010-08-24

申请号：US10831502

申请日：2004-04-23

申请人： Robert F. Payne ,  Bhavesh G. Bhakta

发明人： Robert F. Payne ,  Bhavesh G. Bhakta

IPC分类号： H04Q1/20 ,  H04B3/46 ,  H04B17/00

CPC分类号： G01R31/31715 ,  H04L25/03057

摘要： A circuit and method for evaluating serializer deserializer (SERDES) performance that is particularly advantageous when the SERDES has a decision feedback equalizer (DFE). In one embodiment, the circuit has a data processing path and an operational feedback loop coupled to said data processing path and containing an equalizer, perhaps a DFE. In that embodiment, the circuit includes an eye scanning circuit coupled to said data processing path but separate from said equalizer and configured to measure at least one dimension of an eye relative to which said equalizer is configured for operation without substantially affecting said operation.

摘要翻译： 用于评估串行器解串器（SERDES）性能的电路和方法，当SERDES具有判决反馈均衡器（DFE）时特别有利。 在一个实施例中，电路具有耦合到所述数据处理路径并且包含均衡器（可能是DFE）的数据处理路径和操作反馈回路。 在该实施例中，电路包括耦合到所述数据处理路径但与所述均衡器分离的眼睛扫描电路，并配置成测量眼睛的至少一个尺寸，相对于该尺寸，所述均衡器构造成用于操作而基本上不影响所述操作。

公开(公告)号：US07277828B2

公开(公告)日：2007-10-02

申请号：US10777238

申请日：2004-02-12

申请人： Sridhar Ramaswamy ,  Song Wu ,  Bhavesh G. Bhakta

发明人： Sridhar Ramaswamy ,  Song Wu ,  Bhavesh G. Bhakta

IPC分类号： G06F15/00 ,  G06F19/00

CPC分类号： H04L1/24 ,  H04L1/203 ,  H04L25/0212

摘要： A method, and associated storage medium containing software and a system, includes extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.

摘要翻译： 包括软件和系统的方法和相关联的存储介质包括从表征通信信道的参数中提取时域脉冲响应，基于脉冲响应产生输出电压的概率分布函数（PDF）; 并基于最终概率分布函数计算误码率和电压余量之间的关系。 生成输出电压的PDF可以包括以下动作中的一个或多个：将脉冲响应量化为多个量化电平，为量化电平分配抽头并且确定分配给每个量化电平的抽头数量，确定容许电压电平 并且确定每个可允许电压电平的发生概率，确定每个电压电平的PDF; 并卷积所有PDF的各种电压电平，以获得输出电压的PDF。

公开(公告)号：US20110102083A1

公开(公告)日：2011-05-05

申请号：US12613202

申请日：2009-11-05

申请人： Bhavesh G. Bhakta ,  Mark W. Morgan

发明人： Bhavesh G. Bhakta ,  Mark W. Morgan

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2200/408 ,  H03F2200/513 ,  H03F2203/45644 ,  H03F2203/45648 ,  H03F2203/45702 ,  H04L25/028

摘要： Traditionally, complementary metal oxide semiconductor (CMOS) and bipolar transistors have been separately employed in low voltage differential signal (LVDS) drivers. Here, a hybridized LVDS driver is provided with an input stage that uses CMOS transistors and output stages that use bipolar transistors. As a result of this hybridization, the LVDS driver has superior functional characteristics compared to conventional LVDS drivers as well as being able to function with a supply range between about 1.8V and 3.3V.

摘要翻译： 传统上，互补金属氧化物半导体（CMOS）和双极晶体管已经分别用于低电压差分信号（LVDS）驱动器。 这里，混合LVDS驱动器具有使用CMOS晶体管和使用双极晶体管的输出级的输入级。 作为这种杂交的结果，与传统的LVDS驱动器相比，LVDS驱动器具有优异的功能特性，并且能够在约1.8V和3.3V之间的电源范围内工作。

公开(公告)号：US07443913B2

公开(公告)日：2008-10-28

申请号：US10777612

申请日：2004-02-12

申请人： Bhavesh G. Bhakta ,  Sridhar Ramaswamy ,  Robert F. Payne ,  Song Wu

发明人： Bhavesh G. Bhakta ,  Sridhar Ramaswamy ,  Robert F. Payne ,  Song Wu

IPC分类号： H03K5/159

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

摘要翻译： 均衡器包括采样器，滤波器和夏季。 采样器采样表示输入通信信号的信号，以确定具有通信设备数据速率的数字判定输出信号。 滤波器从采样器接收数字判定输出信号，并从中产生均衡信号。 夏天耦合到采样器和滤波器，并将输入通信信号与均衡信号组合在一起。 此外，多个时钟控制与采样器相关联的定时。 这些时钟具有小于数字决策输出信号的预定数据速率的频率。

公开(公告)号：US07315182B2

公开(公告)日：2008-01-01

申请号：US10778455

申请日：2004-02-13

申请人： Robert Floyd Payne ,  Bhavesh G. Bhakta ,  Richard Simpson

发明人： Robert Floyd Payne ,  Bhavesh G. Bhakta ,  Richard Simpson

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： G01S1/00

摘要： A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

摘要翻译： 串行数据接收器电路包括一对差分输入节点和接收器电路以及耦合在差分输入节点之间的终端电路。 终端电路包括一个共模节点。 共模控制电路连接到共模节点，并且呈现基本为零的输出阻抗。 在这样做时，共模控制电路向终端电路的共模节点提供共模电压，其表现出基本上理想的共模信号的终止和差分输入节点上的可忽略的负载。 在另一方面，提供了选择电路，其在测试操作模式期间选择性地将单端或差分测试信号传送到差分输入节点。 选择电路有助于观察接收机电路内的信号。

公开(公告)号：US06738206B2

公开(公告)日：2004-05-18

申请号：US09990962

申请日：2001-11-14

申请人： Younggyun Kim ,  Bhavesh G. Bhakta ,  David R. Gruetter

发明人： Younggyun Kim ,  Bhavesh G. Bhakta ,  David R. Gruetter

IPC分类号： G11B2020

CPC分类号： G11B20/10009 ,  G11B21/025 ,  H03L7/087 ,  H03L7/091

摘要： A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining the first phase error during a first time period, a second phase detector to detect a second phase error between the input signals, the second phase detector obtaining the second phase error during a second time period, the second time period being longer than the first time period, and a compensation circuit to compensate the first phase error with a portion of the second phase error signal.

摘要翻译： 一种用于锁相环的电路，包括检测输入信号之间的第一相位误差的第一相位检测器，第一相位检测器在第一时间段期间获得第一相位误差;第二相位检测器，用于检测第一相位误差， 所述输入信号，所述第二相位检测器在第二时间段期间获得所述第二相位误差，所述第二时间段长于所述第一时间周期;以及补偿电路，用于补偿所述第一相位误差与所述第二相位误差信号的一部分 。

公开(公告)号：US06256159B1

公开(公告)日：2001-07-03

申请号：US09323595

申请日：1999-06-01

申请人： Bhavesh G. Bhakta

发明人： Bhavesh G. Bhakta

IPC分类号： G11D509

CPC分类号： G11B20/10009

摘要： A circuit (10) and method for dibit detection in a mass data storage device includes concurrently operating magnitude (16), polarity (18), and peak value (20) qualification circuits. The magnitude qualification circuit (16) produces a magnitude qualification output signal when a magnitude of the read back signal exceeds a predetermined magnitude threshold. The polarity qualification circuit produces a polarity qualification output signal when a polarity of the read back signal is of a predetermined polarity. The peak value qualification circuit produces a peak value qualification output signal at a time at which a peak value of the read back signal occurs during a predetermined period. When the magnitude qualification output signal, the polarity qualification output signal, and the peak value qualification output signals simultaneously occur, a dibit detection signal (118) is produced.

摘要翻译： 在大容量数据存储装置中，用于二进制检测的电路（10）和方法包括同时操作幅度（16），极性（18）和峰值（20）限定电路。 当读回信号的幅度超过预定幅度阈值时，幅度鉴定电路（16）产生幅度鉴定输出信号。 当读回信号的极性为预定极性时，极性鉴定电路产生极性鉴定输出信号。 峰值鉴定电路在预定时段内产生读回信号的峰值的时刻产生峰值鉴定输出信号。 当大小限定输出信号，极性鉴定输出信号和峰值鉴定输出信号同时发生时，产生双位检测信号（118）。

公开(公告)号：US08653856B2

公开(公告)日：2014-02-18

申请号：US13234318

申请日：2011-09-16

申请人： Oliver Piepenstock ,  Andreas Bock ,  Bhavesh G. Bhakta

发明人： Oliver Piepenstock ,  Andreas Bock ,  Bhavesh G. Bhakta

IPC分类号： H03K19/094 ,  H03B1/00

CPC分类号： H03K19/018528

摘要： A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

摘要翻译： 提供缓冲区。 缓冲器包括在第一输出节点串联耦合的第一开关和第二开关，第三开关和第四开关，其在第二输出节点串联耦合，第一电流源和第二电流源。 第一电流源与一侧耦合到第一开关和第三开关，并且另一侧耦合到第一电源电压，第二电流源与一侧耦合到第二开关和第四开关，并且第二侧耦合到 第二电源电压。 第一电流源被配置为在第一操作模式和第二操作中调整输出摆幅。 第二电流源被配置为在第一操作模式中调节输出信号的共模电压电平，并且在第二操作模式中提供最大串联电阻。

公开(公告)号：US20120074987A1

公开(公告)日：2012-03-29

申请号：US13234318

申请日：2011-09-16

申请人： Oliver Piepenstock ,  Andreas Bock ,  Bhavesh G. Bhakta

发明人： Oliver Piepenstock ,  Andreas Bock ,  Bhavesh G. Bhakta

IPC分类号： H03K3/00

CPC分类号： H03K19/018528

摘要： A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

摘要翻译： 提供缓冲区。 缓冲器包括在第一输出节点串联耦合的第一开关和第二开关，第三开关和第四开关，其在第二输出节点串联耦合，第一电流源和第二电流源。 第一电流源与一侧耦合到第一开关和第三开关，并且另一侧耦合到第一电源电压，第二电流源与一侧耦合到第二开关和第四开关，并且第二侧耦合到 第二电源电压。 第一电流源被配置为在第一操作模式和第二操作中调整输出摆幅。 第二电流源被配置为在第一操作模式中调节输出信号的共模电压电平，并且在第二操作模式中提供最大串联电阻。

公开(公告)号：US06636120B2

公开(公告)日：2003-10-21

申请号：US09991680

申请日：2001-11-21

申请人： Bhavesh G. Bhakta ,  Younggyun Kim

发明人： Bhavesh G. Bhakta ,  Younggyun Kim

IPC分类号： H03L7093

CPC分类号： G11B20/1025 ,  G11B20/10037 ,  G11B20/1403 ,  H03L7/091 ,  H03L7/093

摘要： A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.