公开(公告)号：US20190303281A1

公开(公告)日：2019-10-03

申请号：US15941468

申请日：2018-03-30

申请人： Amin Firoozshahian ,  Vedaraman Greetha ,  Andreas Kleen ,  Stephen Van Doren ,  Omid Azizi ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert

发明人： Amin Firoozshahian ,  Vedaraman Greetha ,  Andreas Kleen ,  Stephen Van Doren ,  Omid Azizi ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert

IPC分类号： G06F12/02 ,  G06F12/06

摘要： Various systems and methods for controlling memory traffic flow rate are described herein. A system for computer memory management, the system comprising: rate control circuitry to: receive a rate exceeded signal from monitoring circuitry, the rate exceeded signal indicating that memory traffic flow from a traffic source exceeds a threshold; receive a distress signal from a memory controller that interfaces with a memory device, the distress signal indicating that the memory device is oversubscribed; and implement throttle circuitry to throttle the memory traffic flow from the traffic source when the rate exceeded signal and the distress signal are both asserted.

公开(公告)号：US20190121837A1

公开(公告)日：2019-04-25

申请号：US16230814

申请日：2018-12-21

申请人： OMID AZIZI ,  CHEN KOREN ,  NITIN GAREGRAT

发明人： OMID AZIZI ,  CHEN KOREN ,  NITIN GAREGRAT

IPC分类号： G06F17/16 ,  G06N3/02

摘要： An apparatus and method for a masked multiply instruction to support neural network pruning operations. For example, one embodiment of a processor comprises: a decoder to decode a matrix multiplication with masking (GEMM) instruction identifying a destination matrix register to store a result, and source registers storing an A-matrix, a B-matrix, and a matrix mask; execution circuitry to execute the GEMM instruction, the execution circuitry to multiply a plurality of B-matrix elements with a plurality of A-matrix elements, each of the B-matrix elements associated with a mask value in the matrix mask, wherein if the mask value is set to a first value, then the execution circuitry is to multiply the B-matrix element with one or more of the A-matrix elements to generate a first partial result, and if the mask value is set to a second value, then the execution circuitry is to multiply an alternate B-matrix element with a one or more of the A-matrix elements to generate a second partial result.

公开(公告)号：US20190213120A1

公开(公告)日：2019-07-11

申请号：US15868819

申请日：2018-01-11

申请人： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

发明人： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

IPC分类号： G06F12/02 ,  G06F9/50 ,  G06F3/06

CPC分类号： G06F12/0246 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0641 ,  G06F3/065 ,  G06F9/5016 ,  G06F12/0292

摘要： Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

公开(公告)号：US20190354487A1

公开(公告)日：2019-11-21

申请号：US15980523

申请日：2018-05-15

申请人： Vijay Bahirji ,  Amin Firoozshahian ,  Mahesh Madhav ,  Toby Opferman ,  Omid Azizi

发明人： Vijay Bahirji ,  Amin Firoozshahian ,  Mahesh Madhav ,  Toby Opferman ,  Omid Azizi

IPC分类号： G06F12/1009

摘要： A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.

公开(公告)号：US20190212935A1

公开(公告)日：2019-07-11

申请号：US15868787

申请日：2018-01-11

申请人： Chandan Egbert ,  Amin Firoozshahian ,  Mahesh Maddury ,  John Stevenson ,  Henk Neefs ,  Omid Azizi

发明人： Chandan Egbert ,  Amin Firoozshahian ,  Mahesh Maddury ,  John Stevenson ,  Henk Neefs ,  Omid Azizi

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868

摘要： Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

公开(公告)号：US20190042461A1

公开(公告)日：2019-02-07

申请号：US15958591

申请日：2018-04-20

申请人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

发明人： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38

摘要： A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

公开(公告)号：US20190042237A1

公开(公告)日：2019-02-07

申请号：US16016278

申请日：2018-06-22

申请人： Omid AZIZI ,  Guy BOUDOUKH ,  Tony WERNER ,  Andrew YANG ,  Michael ROTZIN ,  Chen KOREN ,  Eriko NURVITADHI

发明人： Omid AZIZI ,  Guy BOUDOUKH ,  Tony WERNER ,  Andrew YANG ,  Michael ROTZIN ,  Chen KOREN ,  Eriko NURVITADHI

IPC分类号： G06F9/30 ,  G06F17/16 ,  G06F9/38

摘要： Disclosed embodiments relate to sparse matrix multiplication (SMM) acceleration using column folding and squeezing. In one example, a processor, in response to a SMM instruction having fields to specify locations of first, second, and output matrices, the second matrix being a sparse matrix, uses execution circuitry to pack the second matrix by replacing one or more zero-valued elements with non-zero elements yet to be processed, each of the replaced elements further including a field to identify its logical position within the second matrix, and, the execution circuitry further to, for each non-zero element at row M and column K of the specified first matrix, generate a product of the element and each corresponding non-zero element at row K, column N of the packed second matrix, and accumulate each generated product with a previous value of a corresponding element at row M and column N of the specified output matrix.