公开(公告)号：US20210406195A1

公开(公告)日：2021-12-30

申请号：US17473468

申请日：2021-09-13

Applicant: Rupin Vakharwala ,  Vedvyas Shanbhogue

Inventor： Rupin Vakharwala ,  Vedvyas Shanbhogue

IPC: G06F12/1027 ,  G06F13/16 ,  G06F13/42

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to PCIe Address Translation Service (ATS) to allow devices to have a DevTLB that caches address translation (per page) information in conjunction with a Device ProcessInfoCache (DevPIC) that will store process specific information. Other embodiments may be described and/or claimed.

公开(公告)号：US20190042461A1

公开(公告)日：2019-02-07

申请号：US15958591

申请日：2018-04-20

Applicant: Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

Inventor： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38

Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

公开(公告)号：US20070005870A1

公开(公告)日：2007-01-04

申请号：US11171993

申请日：2005-06-29

Applicant: Gilbert Neiger ,  Steven Bennett ,  Andrew Anderson ,  Dion Rodgers ,  David Koufaty ,  Richard Uhlig ,  Camron Rust ,  Larry Smith ,  Rupin Vakharwala

Inventor： Gilbert Neiger ,  Steven Bennett ,  Andrew Anderson ,  Dion Rodgers ,  David Koufaty ,  Richard Uhlig ,  Camron Rust ,  Larry Smith ,  Rupin Vakharwala

IPC: G06F21/00

CPC classification number: G06F12/1009 ,  G06F9/45537

Abstract: A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.

Abstract translation: 能够在主机中操作的处理器，包括用于支持由处理器进行物理存储器访问的多种存储器类型的存储器管理逻辑，以及虚拟化支持逻辑，以通过以下方式来确定用于引用存储器位置的主机存储器类型 至少部分地基于存储在主机的虚拟化支持系统（扩展存储器类型字段）的扩展寻呼表的条目中的存储器类型字段来在处理器上执行的虚拟机中的客户端，以确定客户机存储器类型 用于引用存储器位置，并且基于主机存储器类型和来宾存储器类型中的至少一个来确定有效的存储器类型。

公开(公告)号：US20190228145A1

公开(公告)日：2019-07-25

申请号：US16370921

申请日：2019-03-30

Applicant: Vedvyas Shanbhogue ,  Ravi Sahita ,  Abhishek Basak ,  Pradeep Pappachan ,  Utkarsh Kakaiya ,  Ravi Sahita ,  Rupin Vakharwala

Inventor： Vedvyas Shanbhogue ,  Ravi Sahita ,  Abhishek Basak ,  Pradeep Pappachan ,  Utkarsh Kakaiya ,  Ravi Sahita ,  Rupin Vakharwala

IPC: G06F21/44 ,  G06F13/16 ,  G06F3/06

Abstract: Systems, methods, and apparatuses relating to performing an attachment of an input-output memory management unit (IOMMU) to a device, and a verification of the attachment. In one embodiment, a protocol and IOMMU extensions are used by a secure arbitration mode (SEAM) module and/or circuitry to determine if the IOMMU that is attached to the device requested to be mapped to a trusted domain.

公开(公告)号：US20230401061A1

公开(公告)日：2023-12-14

申请号：US18126920

申请日：2023-03-27

Applicant: Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

Inventor： Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/30098 ,  G06F15/80 ,  G06F9/5005 ,  G06F9/4812

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US20210357221A1

公开(公告)日：2021-11-18

申请号：US17359337

申请日：2021-06-25

Applicant: Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

Inventor： Ashok RAJ ,  Andreas KLEEN ,  Gilbert NEIGER ,  Beeman STRONG ,  Jason BRANDT ,  Rupin VAKHARWALA ,  Jeff HUXEL ,  Larisa NOVAKOVSKY ,  Ido OUZIEL ,  Sarathy JAYAKUMAR

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.