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    Scan register and methods of using the same
    2.
    发明授权
    Scan register and methods of using the same 有权
    扫描寄存器和使用方法

    公开(公告)号：US07457998B1

    公开(公告)日：2008-11-25

    申请号：US11033059

    申请日：2005-01-07

    申请人： Sandeep Bhatia ,  Oriol Roig

    发明人： Sandeep Bhatia ,  Oriol Roig

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541

    摘要： An improved scan register and methods of using the same have been disclosed. In one embodiment, the improved scan register includes a master latch having a data input, a data output, and a control input. The control input is coupled to a clock signal. The master latch is operable to store data. The improved scan register further includes a scan latch having a data input, a data output, and a control input. The data input of the scan latch is coupled to the data output of the master latch. The scan latch is operable to receive and to store the data from the master latch in response to the scan latch being in a scan mode. The improved scan register may further include a functional latch having a data input, a data output, and a control input. The data input of the functional latch is coupled to the data output of the master latch. The functional latch is operable to receive and to store the data from the master latch in response to the functional latch being in a functional mode. Other embodiments have been claimed and described.

    摘要翻译： 已经公开了改进的扫描寄存器及其使用方法。 在一个实施例中，改进的扫描寄存器包括具有数据输入，数据输出和控制输入的主锁存器。 控制输入​​耦合到时钟信号。 主锁存器可操作以存储数据。 改进的扫描寄存器还包括具有数据输入，数据输出和控制输入的扫描锁存器。 扫描锁存器的数据输入耦合到主锁存器的数据输出端。 响应于扫描锁存器处于扫描模式，扫描锁存器可操作以接收并存储来自主锁存器的数据。 改进的扫描寄存器还可以包括具有数据输入，数据输出和控制输入的功能锁存器。 功能锁存器的数据输入耦合到主锁存器的数据输出端。 响应于功能锁存器处于功能模式，功能锁存器可操作以接收并存储来自主锁存器的数据。 已经要求和描述了其它实施例。

    Methods and apparatus for scan testing of integrated circuits with scan registers
    3.
    发明授权
    Methods and apparatus for scan testing of integrated circuits with scan registers 失效
    具有扫描寄存器的集成电路的扫描测试方法和装置

    公开(公告)号：US07743298B1

    公开(公告)日：2010-06-22

    申请号：US12258421

    申请日：2008-10-26

    申请人： Sandeep Bhatia ,  Oriol Roig

    发明人： Sandeep Bhatia ,  Oriol Roig

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541

    摘要： In one embodiment of the invention, a method of scan testing an integrated circuit is disclosed. The method includes scanning a first test vector and a second test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch, a scan latch, and a functional latch; and applying the first and the second test vectors sequentially in a delay fault test via the plurality of scan registers to a combinational logic circuit coupled to the plurality of scan registers.

    摘要翻译： 在本发明的一个实施例中，公开了一种集成电路的扫描测试方法。 该方法包括将第一测试向量和第二测试向量顺序地扫描到串联耦合在一起的多个扫描寄存器，多个扫描寄存器中的每一个包括主锁存器，扫描锁存器和功能锁存器; 以及将第一测试向量和第二测试向量顺序地经由多个扫描寄存器的延迟故障测试应用到耦合到所述多个扫描寄存器的组合逻辑电路。

    Apparatus for scan testing of integrated circuits with scan registers
    4.
    发明授权
    Apparatus for scan testing of integrated circuits with scan registers 有权
    具有扫描寄存器的集成电路的扫描测试装置

    公开(公告)号：US08078925B1

    公开(公告)日：2011-12-13

    申请号：US12778041

    申请日：2010-05-11

    申请人： Sandeep Bhatia ,  Oriol Roig

    发明人： Sandeep Bhatia ,  Oriol Roig

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541

    摘要： In one embodiment of the invention, an apparatus for scan testing an integrated circuit is provided. The apparatus includes a combinational logic network; and a device for reducing gate switching in the combinational logic network to reduce power consumption during a scan test on the combinational logic network. The device for reducing gate switching in the combinational logic network includes a device for periodically isolating scan data from the combination logic network; and a device for periodically holding functional data coupled into the combinational network substantially steady. In one embodiment of the invention, the device for reducing gate switching in the combinational logic network is a plurality of serially coupled scan registers each having a pair of opposed controlled outputs with one controlled output providing scan output data and another controlled output providing functional data to the combinational logic network.

    摘要翻译： 在本发明的一个实施例中，提供了一种用于集成电路的扫描测试的装置。 该装置包括组合逻辑网络; 以及用于减少组合逻辑网络中的门切换以在组合逻辑网络的扫描测试期间降低功耗的装置。 用于减少组合逻辑网络中的门切换的装置包括用于周期性地从组合逻辑网络隔离扫描数据的装置; 以及用于周期性地保持耦合到组合网络中的功能数据基本稳定的设备。 在本发明的一个实施例中，用于减少组合逻辑网络中的栅极切换的装置是多个串联耦合的扫描寄存器，每个扫描寄存器具有一对相对的受控输出，其中一个受控输出提供扫描输出数据，另一个控制输出提供功能数据 组合逻辑网络。