公开(公告)号：US20070108517A1

公开(公告)日：2007-05-17

申请号：US11273222

申请日：2005-11-12

申请人： You-Kuo Wu ,  Fu-Hsin Chen ,  P.Y. Chiang ,  An-Min Chiang

发明人： You-Kuo Wu ,  Fu-Hsin Chen ,  P.Y. Chiang ,  An-Min Chiang

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42356

摘要： A power metal-oxide semiconductor device provides an P-type base region that includes the N+ device source and is biased differently than the P-type substrate by application of an electrical load. In one embodiment, an LDMOS device with a NPN configuration is used but the coupling of the device source to the base contact prevents the NPN parasitic device from operating. The P-type base is formed in an N-well that separates the base from the P-type substrate and surrounding P-wells. Vertical punch-through is prevented by a high-impurity N+ buried layer that separates the N-well from the P-type substrate.

摘要翻译： 功率金属氧化物半导体器件提供包括N +器件源的P型基极区域，并且通过施加电负载而不同于P型衬底的偏置。 在一个实施例中，使用具有NPN配置的LDMOS器件，但是器件源与基极接触的耦合防止了NPN寄生器件的工作。 P型基底形成在将P基底和P型基底分隔开的N阱中。 通过将N阱与P型衬底分离的高杂质N +掩埋层防止垂直穿通。