Abstract:
Systems and methods for switch prefetch in multicore computer chips can allow a programmer to tailor operations of a computer program to available data. Control-flow decisions can be made by the program based on the availability of data in a cache. For example, a new instruction in a processor instruction set can receive a list comprising pairs of data addresses and code addresses. The processor can look for data items corresponding to the listed data addresses, and find the first available data item in the cache. When a cached data item is found, control is transferred to the code address supplied in the table. If no data is in the cache, then the processor can stall until the most quickly fetched data item is available.
Abstract:
A system for providing augmented reality detects foreground occluders in an image of a video stream. One or more virtual objects are then rendered appropriately with respect to the occluders. Location information associated with the image is used to retrieve a three dimensional representation of the location where the image was taken. Features that are expected to appear in the image based on the three dimensional location but that cannot be located are used to determine regions of the image that are likely to include foreground occluders. Pixels in these regions are used to train a color model that classifies pixels as either part of the background of the image or part of one or more foreground occluders. The pixels in the image are classified using the model, and one or more virtual objects are rendered so that they appear behind any foreground occluders.
Abstract:
Systems and methods for scheduling thread execution among a plurality of processors based on evaluation of memory access data can comprise collecting and evaluating memory access data corresponding to two or more threads. Based on the evaluation results, it can be determined whether to prospectively assign the two or more threads to execute on different processors when they are to be executing simultaneously. A scheduler can select a processor to execute a thread, and consult an identity of threads to determine whether to assign them to the same or a different processor. The scheduler may also adjust a scheduling frequency for better thread compatibility on a single processor.
Abstract:
A system for providing augmented reality detects foreground occluders in an image of a video stream. One or more virtual objects are then rendered appropriately with respect to the occluders. Location information associated with the image is used to retrieve a three dimensional representation of the location where the image was taken. Features that are expected to appear in the image based on the three dimensional location but that cannot be located are used to determine regions of the image that are likely to include foreground occluders. Pixels in these regions are used to train a color model that classifies pixels as either part of the background of the image or part of one or more foreground occluders. The pixels in the image are classified using the model, and one or more virtual objects are rendered so that they appear behind any foreground occluders.
Abstract:
Network congestion avoidance within aggregated channels is disclosed. In one embodiment, a method first transmits a packet associated with a first channel of a plurality of related channels from a source protocol layer (e.g., a source IP layer) of a source through a network (e.g., the Internet). Next, the method triggers an ECN event by the packet at the network. Finally, at least one channel is determined to have decreased packets transmitted therethrough, in response to the triggering of the ECN event (e.g., based on a congestion pricing criteria).
Abstract:
Systems and methods for switch prefetch in multicore computer chips can allow a programmer to tailor operations of a computer program to available data. Control-flow decisions can be made by the program based on the availability of data in a cache. For example, a new instruction in a processor instruction set can receive a list comprising pairs of data addresses and code addresses. The processor can look for data items corresponding to the listed data addresses, and find the first available data item in the cache. When a cached data item is found, control is transferred to the code address supplied in the table. If no data is in the cache, then the processor can stall until the most quickly fetched data item is available.
Abstract:
Network congestion avoidance within aggregated channels is disclosed. In one embodiment, a method first transmits a packet associated with a first channel of a plurality of related channels from a source protocol layer (e.g., a source IP layer) of a source through a network (e.g., the Internet). Next, the method triggers an ECN event by the packet at the network. Finally, at least one channel is determined to have decreased packets transmitted therethrough, in response to the triggering of the ECN event (e.g., based on a congestion pricing criteria).