公开(公告)号：US09006057B2

公开(公告)日：2015-04-14

申请号：US13989164

申请日：2012-07-31

申请人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

发明人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

IPC分类号： H01L21/36 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/265

CPC分类号： H01L21/30604 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.

摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，该方法包括：在衬底上形成栅叠层; 在栅极堆叠的两侧蚀刻衬底以形成C形源极/漏极沟槽; 并对C形源极/漏极沟槽进行湿式蚀刻以形成S形的源极/漏极沟槽。 通过该方法，能够有效地增加施加于沟道区域的应力，精确地控制源极/漏极沟槽的深度，并且可以减小沟槽的侧壁和底部的粗糙度，从而通过蚀刻C来减少缺陷 形状的源极/漏极沟槽，然后进一步湿法蚀刻它们以形成源极/漏极沟槽。

公开(公告)号：US20140057404A1

公开(公告)日：2014-02-27

申请号：US13989164

申请日：2012-07-31

申请人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

发明人： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

IPC分类号： H01L21/306 ,  H01L29/66

CPC分类号： H01L21/30604 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.

摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，该方法包括：在衬底上形成栅叠层; 在栅极堆叠的两侧蚀刻衬底以形成C形源极/漏极沟槽; 并对C形源极/漏极沟槽进行湿蚀刻以形成Σ型源极/漏极沟槽。 通过该方法，能够有效地增加施加于沟道区域的应力，精确地控制源极/漏极沟槽的深度，并且可以减小沟槽的侧壁和底部的粗糙度，从而通过蚀刻C来减少缺陷 形状的源极/漏极沟槽，然后进一步湿法蚀刻它们以形成Sigma形状的源极/漏极沟槽。