公开(公告)号：US06885961B2

公开(公告)日：2005-04-26

申请号：US10090585

申请日：2002-02-28

申请人： Peter Breger ,  Grady Borders

发明人： Peter Breger ,  Grady Borders

IPC分类号： G01R31/319 ,  G06F11/26 ,  G06F19/00

CPC分类号： G01R31/31922 ,  G01R31/31928

摘要： A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.

摘要翻译： 公开了一种并行测试多个半导体器件的混合测试器架构。 混合测试器架构包括具有数据输入电路和时钟输入电路的每引脚格式化电路以及耦合到时钟输入电路的共享定时电路。 共享定时电路产生编程定时信号。 每针数据电路耦合到数据输入电路，并产生与各个器件引脚相关联的驱动数据和预期数据值。 每针式格式化电路响应编程的定时信号，以根据每针数据产生测试仪波形。

公开(公告)号：US6137310A

公开(公告)日：2000-10-24

申请号：US253175

申请日：1999-02-19

申请人： Peter Breger

发明人： Peter Breger

IPC分类号： G01R31/319 ,  H03K19/00

CPC分类号： G01R31/31924

摘要： A tristate circuit for driving three signal levels to a pin of a device-under-test is disclosed. The tristate circuit includes a driver having an output at a first signal level and adapted for coupling to the pin. A first switching unit couples to the output and responds to a programmed signal. The first switching unit operates to selectively alter the first signal level to a second signal level. A second switching unit connects serially to the first switch. The second switching unit responds to a second programmed signal and operates to cooperate with the first switch to alter the second signal level to a third signal level.

摘要翻译： 公开了一种用于将三信号电平驱动到待测器件的引脚的三态电路。 三态电路包括具有第一信号电平的输出并适于耦合到引脚的驱动器。 第一切换单元耦合到输出并响应于编程信号。 第一开关单元操作以选择性地将第一信号电平改变到第二信号电平。 第二开关单元串联连接到第一开关。 第二开关单元响应于第二编程信号并且操作以与第一开关协作以将第二信号电平改变为第三信号电平。

公开(公告)号：US06360180B1

公开(公告)日：2002-03-19

申请号：US09309134

申请日：1999-05-10

申请人： Peter Breger

发明人： Peter Breger

IPC分类号： G01D300

CPC分类号： G01R31/31924

摘要： A driver for applying a deterministic waveform along a lossy transmission path to a device-under-test is disclosed. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.

摘要翻译： 公开了一种用于沿着有损传输路径将确定性波形应用于被测器件的驱动器。 驱动器包括用于在输出节点处产生基本方波信号的信号发生器，以及耦合到输出节点的注入器，用于修改方波信号以预补偿沿损耗路径的预期损耗。