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1.发明授权Graduated multiple collector structure for inverted vertical bipolar transistors 失效用于反转垂直双极晶体管的分级多个收集器结构
公开(公告)号：US4084174A
公开(公告)日：1978-04-11
申请号：US657439
申请日：1976-02-12
CPC分类号： H01L27/0233
摘要： A graduated multiple collector structure for inverted vertical bipolar transistors, integrated injection logic devices and the like. The invention increases the gain of more distant collectors toward which current flows laterally past intervening collectors from a base contact, and injector or the like. The series resistance drop and the current loss in the base-emitter junction are compensated for by progressively increasing the effective area of collectors further distant from the source of the base current. Although the graduated collector structure is applicable to a wide variety of semiconductor devices, it is particularly well suited for use in oxide-isolated integrated injection logic gates. A mathematical model is provided which can help to optimize designs incorporating the graduated collector structure.
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公开(公告)号：US3984670A
公开(公告)日：1976-10-05
申请号：US562378
申请日：1975-03-26
CPC分类号： G06F7/575 , G06F15/7896 , G06F2207/3896 , G06F7/4991
摘要： An arithmetic logic register stack device is provided on a single semiconductor chip, which device comprises a building block for digital systems. The device of this invention is expandable, which enables performing operations with binary numbers greater than that with which a single device is capable of performing. Unique circuit design is provided for multiple use of connector pins to the semiconductor device, thereby allowing for an increase in the complexity of the circuits that can be integrated onto a single semiconductor chip or placed into a package with a given number of pins.
摘要翻译： 在单个半导体芯片上提供算术逻辑寄存器堆栈装置，该装置包括用于数字系统的构建块。 本发明的设备是可扩展的，其能够执行大于单个设备能够执行的二进制数的操作。 提供独特的电路设计用于多个使用连接器引脚到半导体器件，从而允许增加可集成到单个半导体芯片上的电路的复杂性，或者放置在具有给定数量引脚的封装中。
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