公开(公告)号：US4258333A

公开(公告)日：1981-03-24

申请号：US44728

申请日：1979-06-01

申请人： Pierre Demuliere ,  Pierre Heins

发明人： Pierre Demuliere ,  Pierre Heins

IPC分类号： H03L7/18 ,  H03L7/113 ,  H03L7/16 ,  H03L7/193 ,  H03L7/197 ,  H03L7/08

CPC分类号： H03L7/113 ,  H03L7/1974 ,  H03L7/193

摘要： This synthesizer comprises a phase-locked main loop, a frequency searching loop, a first digital loop for forming steps equal to the reference frequency F and a second digital loop for forming steps equal to the frequency F/Q, Q being an integer. According to the invention this synthesizer further comprises a third digital loop which acts on the setting of the steps having value F for forming the steps having a frequency F/R, R being an integer near Q. The elementary frequency step of the synthesizer has the frequency value .vertline.F/Q-F/R.vertline. or a value equal to a submultiple of the last-mentioned value. This spurious modulation at the frequency OR/.vertline.Q-R.vertline. F of the output signal of the phase comparator has an amplitude which is sufficiently low to make filtering unnecessary.

摘要翻译： 该合成器包括锁相主环路，频率搜索环路，用于形成等于参考频率F的步长的第一数字环路和用于形成等于频率F / Q的步长的第二数字环路，Q为整数。 根据本发明，该合成器还包括第三数字环路，其作用于具有值F的步骤的设置，用于形成具有频率F / R的步骤，R是接近Q的整数。合成器的基本频率步长具有 频率值| F / QF / R |或等于最后提到的值的一个数的值。 在相位比较器的输出信号的频率OR / | Q-R | F处的这种杂散调制具有足够低的幅度，从而不需要滤波。