Dual-purpose I/O circuit in a combined LINK/PHY integrated circuit
    1.
    发明授权
    Dual-purpose I/O circuit in a combined LINK/PHY integrated circuit 失效
    组合的LINK / PHY集成电路中的双用途I / O电路

    公开(公告)号:US5929655A

    公开(公告)日:1999-07-27

    申请号:US824203

    申请日:1997-03-25

    IPC分类号: G06F13/40 A03K19/0175

    CPC分类号: G06F13/4072

    摘要: A dual-purpose I/O circuit for use in an integrated circuit having a primary circuit is provided. The dual-purpose I/O circuit includes two conducting pads, two single-ended I/O cells and one differential I/O cell. Several dual-purpose I/O circuits can be used within a single integrated circuit to support both single-ended and/or differential mode I/O signaling between external circuits and devices and a primary circuit within the integrated circuit. Within each dual-purpose I/O circuit, a first single-ended I/O cells is connected to a first conducting pad, a second single-ended I/O cell is connected to the second conducting pad and a differential I/O cell is connected to the both the first single-ended and second single-ended I/O cells and to both the first and second conducting pads. A control logic is connected to at least one of the first single-ended, second single-ended and differential I/O cells. The control logic is arranged to selectively enable and disable at least one of the first single-ended, second single-ended and differential I/O cells. The primary circuit can include any digital and/or analog circuit. The primary circuit can include a combined LINK/PHY circuit configured to support IEEE-1394 standard buses and communications.

    摘要翻译: 提供了一种用于具有初级电路的集成电路中的双用途I / O电路。 双通道I / O电路包括两个导电焊盘,两个单端I / O单元和一个差分I / O单元。 可以在单个集成电路中使用多个双用途I / O电路,以支持外部电路和器件之间的单端和/或差分模式I / O信号以及集成电路内的主电路。 在每个双用途I / O电路中,第一单端I / O单元连接到第一导电焊盘,第二单端I / O单元连接到第二导电焊盘和差分I / O单元 连接到第一单端和第二单端I / O单元以及第一和第二导电焊盘。 控制逻辑连接到第一单端,第二单端和差分I / O单元中的至少一个。 控制逻辑被布置为选择性地启用和禁用第一单端,第二单端和差分I / O单元中的至少一个。 主电路可以包括任何数字和/或模拟电路。 主电路可以包括被配置为支持IEEE-1394标准总线和通信的组合的LINK / PHY电路。

    Efficient method and resulting structure for integrated circuits with
flexible I/O interface and power supply voltages
    2.
    发明授权
    Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages 失效
    具有灵活I / O接口和电源电压的集成电路的高效方法和结果

    公开(公告)号:US5646548A

    公开(公告)日:1997-07-08

    申请号:US601375

    申请日:1996-02-14

    IPC分类号: H03K19/0185

    摘要: A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.

    摘要翻译: 半导体集成电路以多于一组VH / VL电压电平接收和发送信号。 集成电路包括核心区域,输入焊盘,输出焊盘,外围电路和多个电源线,每个电源线各自处于电源电压电平V1,V2,V3。 。 。 嗯 集成电路还包括输入电路和输出电路,每一个都具有缓冲器和转换器。 每个电源线的电源电压V1,V2,V3可用性。 。 。 Vm和转换器允许本电路在同一集成电路内传输和接收各种输入信号和输出信号。

    Efficient method and resulting structure for integrated circuits with
flexible I/O interface and power supply voltages
    3.
    发明授权
    Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages 失效
    具有灵活I / O接口和电源电压的集成电路的高效方法和结果

    公开(公告)号:US5521530A

    公开(公告)日:1996-05-28

    申请号:US299004

    申请日:1994-08-31

    IPC分类号: H03K19/0185 H03K19/0175

    摘要: A semiconductor integrated circuit receives and transmits signals at more than one set of VH/VL voltage levels. The integrated circuit includes a core region, an input pad, an output pad, peripheral circuitry, and a plurality of power supply lines each at power supply voltage levels V1, V2, V3 . . . Vm. The integrated circuit also includes input circuitry and output circuitry each of which have buffers and translators. The availability of the power lines each at power supply voltage levels V1, V2, V3 . . . Vm and translators allows for the present circuit to transmit and receive various sets of input signals and output signals, all within the same integrated circuit.

    摘要翻译: 半导体集成电路以多于一组VH / VL电压电平接收和发送信号。 集成电路包括核心区域,输入焊盘,输出焊盘,外围电路和多个电源线,每个电源线各自处于电源电压电平V1,V2,V3。 。 。 嗯 集成电路还包括输入电路和输出电路,每一个都具有缓冲器和转换器。 每个电源线的电源电压V1,V2,V3可用性。 。 。 Vm和转换器允许本电路在同一集成电路内传输和接收各种输入信号和输出信号。