公开(公告)号：US20160254793A1

公开(公告)日：2016-09-01

申请号：US15029777

申请日：2014-11-05

Applicant: Wenjun SU ,  Guangming YIN ,  Quanqing ZHU ,  QUALCOMM INCORPORATED

Inventor： Wenjun SU ,  Guangming YIN ,  Quanqing ZHU

IPC: H03F3/45 ,  H03K5/12

CPC classification number: H03F3/45762 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45609 ,  H03F3/72 ,  H03F2200/555 ,  H03F2200/72 ,  H03F2203/45288 ,  H03F2203/45301 ,  H03F2203/45511 ,  H03F2203/45638 ,  H03F2203/45644 ,  H03F2203/45702 ,  H03K5/12

Abstract: Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.

Abstract translation: 提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。 一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动器放大器，一对n级电路和输入偏差平均电路，其中， n级单元分为两个半块。 输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极至源极电压的偏移。 对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和工作速度。

公开(公告)号：US09401594B2

公开(公告)日：2016-07-26

申请号：US14374498

申请日：2012-02-15

Applicant: Quanqing Zhu ,  Guangming Yin

Inventor： Quanqing Zhu ,  Guangming Yin

IPC: H02H9/00 ,  H02H3/22 ,  H04L25/02

CPC classification number: H02H3/22 ,  H04L25/0272 ,  H04L25/028

Abstract: An integrated circuit device (200) includes a first and second differential I/O pins (TRXP/TRXN) and a surge protection circuit. The surge protection circuit includes a protection transistor, a positive surge detection circuit, and a negative surge detection circuit. The protection transistor is connected between the first and second I/O pins and has a gate to receive a control signal (CTRL). The protection transistor is turned on to connect the I/O pins together if the positive surge detection circuit detects a positive surge energy on either of the I/O pins and/or if the negative surge detection circuit detects a negative surge energy on either of the I/O pins. The surge protection circuit provides increased protection for Ethernet device against undesirable energy in a manner that does not adversely affect the performance of the device.

Abstract translation: 集成电路装置（200）包括第一和第二差分I / O引脚（TRXP / TRXN）和浪涌保护电路。 浪涌保护电路包括保护晶体管，正浪涌检测电路和负浪涌检测电路。 保护晶体管连接在第一和第二I / O引脚之间，并具有接收控制信号（CTRL）的门。 如果正浪涌检测电路检测到任一个I / O引脚上的正浪涌能量和/或如果负浪涌检测电路检测到任何一个的负浪涌能量，则保护晶体管导通以将I / O引脚连接在一起 I / O引脚。 浪涌保护电路以不会对设备性能产生不利影响的方式为以太网设备提供更高的防护性能，防止不需要的能量。