公开(公告)号：US5526500A

公开(公告)日：1996-06-11

申请号：US387960

申请日：1995-02-10

申请人： Darius F. Tanksalvala ,  Eric R. DeLano ,  Patrick Knebel ,  Thomas R. Hotchkiss ,  R. Craig Simpson

发明人： Darius F. Tanksalvala ,  Eric R. DeLano ,  Patrick Knebel ,  Thomas R. Hotchkiss ,  R. Craig Simpson

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/32 ,  G06F9/312

CPC分类号： G06F12/0888 ,  G06F12/0855 ,  G06F9/3824 ,  G06F9/3842

摘要： Pipeline structure that is arranged to allow 1.5 cycle access time for both data and instruction cache without imposing additional instruction step delays than that imposed by data and instruction cache that have 1 cycle access time. Half cycle pulses are produced to allow execution of various instructions in 0.5 cycles. A bypass signal is generated to allow data from a current load instruction to be available for a second subsequent instruction even though the access time for data cache is 1.5 cycles. Additionally, a branch address is available for a third subsequent instruction even though instruction cache access time is 1.5 cycles. The present invention shows the initiation of an instruction step for each cycle and 1.5 cycle access time for cache memory. The present invention can also be implemented by implementing an instruction every 2 cycles and providing 3 cycle access time for cache memory.

摘要翻译： 管道结构被布置为允许数据和指令高速缓存的1.5个周期访问时间，而不施加比具有1个周期访问时间的数据和指令高速缓存所施加的额外的指令阶延迟。 产生半周期脉冲以允许在0.5个周期内执行各种指令。 生成旁路信号以允许来自当前加载指令的数据可用于第二后续指令，即使数据高速缓存的访问时间为1.5个周期。 另外，即使指令高速缓存访​​问时间为1.5个周期，分支地址也可用于第三个后续指令。 本发明示出了针对高速缓冲存储器的每个周期和1.5周期访问时间的指令步骤的启动。 本发明还可以通过每2个周期实现一个指令并为高速缓冲存储器提供3个周期的访问时间来实现。