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公开(公告)号：US09177089B2
公开(公告)日：2015-11-03
申请号：US14474280
申请日：2014-09-01
CPC分类号： G06F17/5045 , G06F17/504
摘要： A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.
摘要翻译： 一种用于电路设计验证的计算机实现的方法和非暂时性计算机可读介质。 对电路设计进行正式验证，以证明电路设计的属性的正确性。 电路设计具有代表电路设计能够影响该特性的信号的一部分的影响锥。 识别电路设计的核心，防爆核心是足以证明属性正确性的影响力的一部分。 产生一个覆盖度量，其指示由基于电路设计的验证核心的属性提供的形式验证覆盖水平。
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公开(公告)号：US20150135150A1
公开(公告)日：2015-05-14
申请号：US14474280
申请日：2014-09-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.
摘要翻译： 一种用于电路设计验证的计算机实现的方法和非暂时性计算机可读介质。 对电路设计进行正式验证，以证明电路设计的属性的正确性。 电路设计具有代表电路设计能够影响该特性的信号的一部分的影响锥。 识别电路设计的核心，防爆核心是足以证明属性正确性的影响力的一部分。 产生一个覆盖度量，其指示由基于电路设计的验证核心的属性提供的形式验证覆盖水平。
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公开(公告)号：US06839884B1
公开(公告)日：2005-01-04
申请号：US09766189
申请日：2001-01-18
CPC分类号： G06F17/5022
摘要： A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.
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公开(公告)号：US06651228B1
公开(公告)日：2003-11-18
申请号：US09566684
申请日：2000-05-08
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.
摘要翻译： 提供了一种便于在设计中的关键点之间分析逻辑信号的预期流程的方法和装置。 根据本发明的一个方面，可以使用新颖的意图驱动验证过程来检测硬件设计缺陷。 首先，接收硬件设计的表示和关于表示中的变量之间的逻辑信号的预期流程的信息。 然后，可以基于关于逻辑信号的预期流程的信息来推断硬件设计中的潜在错误的存在，即（1）将关于逻辑信号的预期流程的信息转换成必须在 硬件设计的顺序是根据逻辑信号的预期流程进行操作，以及（2）在由硬件设计表示的电路的操作期间确定是否可以违反任何检查。
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5.发明授权公开(公告)号：US06704912B2
公开(公告)日：2004-03-09
申请号：US09770068
申请日：2001-01-24
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and apparatus for characterizing information about design attributes is described. The characterization process may begin with determining the dependency among the attributes within a hardware design. Once the dependency is determined, the most relevant information about the hardware design attribute may be highlighted. A user can then focus their attention on the highlighted aspects of the design attribute to draw conclusions about the hardware design as a whole.
摘要翻译： 描述用于表征关于设计属性的信息的方法和装置。 表征过程可以从确定硬件设计中的属性之间的依赖性开始。 一旦确定依赖关系，可以突出显示关于硬件设计属性的最相关信息。 然后，用户可以将注意力集中在设计属性的突出显示的方面，以得出关于整体硬件设计的结论。
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公开(公告)号：US06571375B1
公开(公告)日：2003-05-27
申请号：US09566682
申请日：2000-05-08
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, multiple design verification checks associated with a hardware design are linked by determining dependency reationships among the multiple design verification checks. Each of the design verification checks represent a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals in the hardware design.
摘要翻译： 提供了一种便于在设计中的关键点之间分析逻辑信号的预期流程的方法和装置。 根据本发明的一个方面，通过确定多个设计验证检查之间的依赖关系，链接与硬件设计相关联的多个设计验证检查。 每个设计验证检查都代表了硬件设计根据硬件设计中逻辑信号的预期流程进行操作的必要条件。
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