Abstract:
A method and system for generating and obtaining reliable core dump from a multiple partitioned platform is described. The method generated a system core dump by a first operating system in a first partition, in response to detecting a predetermined event. The core dump may be stored in a shared memory accessible to a plurality of operating systems. An interrupt is sent when a core dump is generated. Upon a detection of the interrupt, the core dump may be accessed by a second operating system in a second partition for analysis. Other embodiments of inventions are described in the claims.
Abstract:
Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.
Abstract:
A method and an apparatus to manage sensors on an autonomous computing network, platform and similar other systems are illustrated. The sensor management module may comprise a sensor management server, a sensor management client and a sensor driver. The sensor management module may discover presence or absence of the sensor on the computing environment and register it with the server management stack automatically.
Abstract:
Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.