公开(公告)号：US07268373B1

公开(公告)日：2007-09-11

申请号：US10947794

申请日：2004-09-23

Applicant: Rajesh Narendra Gupta ,  Farid Nemati

Inventor： Rajesh Narendra Gupta ,  Farid Nemati

IPC: H01L29/745

CPC classification number: H01L27/11 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/74

Abstract: A semiconductor may contain a plurality of circuits each comprising at least one thyristor having a base region. The base region of at least one of the thyristors has a different doping profile than the others. When a bias circuit is used to bias the thyristors, the effect of biasing on the thyristors is found to be affected by the doping profile. In a specific embodiment, the doping concentration is higher near an electrode of the thyristor than near a supporting substrate. The different doping profiles can be achieved by using different ion implant energies.

Abstract translation: 半导体可以包含多个电路，每个电路包括至少一个具有基极区域的晶闸管。 至少一个晶闸管的基极区域具有与其它晶体管不同的掺杂分布。 当偏置电路用于偏置晶闸管时，发现偏置对晶闸管的影响受到掺杂分布的影响。 在具体实施例中，在晶闸管的电极附近的掺杂浓度比在支撑衬底附近更高。 通过使用不同的离子注入能量可以实现不同的掺杂分布。

公开(公告)号：US07054191B1

公开(公告)日：2006-05-30

申请号：US10860194

申请日：2004-06-03

Applicant: Rajesh Narendra Gupta ,  Scott Robins

Inventor： Rajesh Narendra Gupta ,  Scott Robins

IPC: G11C11/39 ,  G11C11/34

CPC classification number: G11C11/39

Abstract: A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same time, the bit lines of the second set of memory cells is set up. After completion of reading of the first set of memory cells, the bit lines of this set of memory cells are set up (while the setting up of the bit lines of the second set of memory cells continues). After the bit lines of both sets of memory cells are set up, the second word line is pulsed. At this time, written into both sets of memory cells begins, which comprises data previously read from the first set of memory cells and new data to be written into the second set of memory cells. It is found that this method reduces the overall write time.

Abstract translation: 第一和第二组存储器单元连接到相同的第一字线和第二字线。 在数据写入开始时，第一个字线被设置。 第一组存储单元读取并临时存储到缓冲器中。 大约在同一时间，第二组存储器单元的位线被建立。 在完成第一组存储单元的读取之后，建立该组存储器单元的位线（同时第二组存储器单元的位线的设置继续）。 在两组存储器单元的位线被建立之后，第二字线被脉冲。 此时，开始写入两组存储器单元，其包括先前从第一组存储器单元读取的数据和要写入第二组存储器单元的新数据。 发现这种方法减少了整个写入时间。