公开(公告)号：US11887648B2

公开(公告)日：2024-01-30

申请号：US17362138

申请日：2021-06-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC分类号： H01L29/66 ,  G11C11/39 ,  G11C11/402 ,  H01L29/749 ,  H01L27/102

CPC分类号： G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

摘要： A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

公开(公告)号：US11798616B2

公开(公告)日：2023-10-24

申请号：US17901982

申请日：2022-09-02

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Masakazu Kakumu ,  Koji Sakui ,  Nozomu Harada

IPC分类号： G11C11/00 ,  G11C11/409 ,  H01L23/00 ,  G11C11/39 ,  H10B12/00

CPC分类号： G11C11/409 ,  G11C11/39 ,  H01L24/45 ,  H10B12/00

摘要： A first semiconductor layer 1 is formed on a substrate, a first impurity layer 3 and a second impurity layer 4 extending in a vertical direction are sequentially disposed on part of the first semiconductor layer 1, their sidewalls and the semiconductor layer 1 are covered by a second gate insulating layer 2, a gate conductor layer 22 and a second insulating layer are disposed in a groove formed there, and a second semiconductor layer 7, n+ layers 6a and 6c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer. Voltage applied to the source line SL, a plate line PL connected to the first gate conductor layer 22, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes in the channel region 12.

公开(公告)号：US20200295284A1

公开(公告)日：2020-09-17

申请号：US16673116

申请日：2019-11-04

申请人： Korea Advanced Institute of Science and Technology

发明人： Yong-Hoon Kim ,  Muhammad Ejaz Khan ,  Juho Lee

IPC分类号： H01L51/05 ,  G11C11/39 ,  H01L51/00 ,  H01L51/10

摘要： A quantum hybridization negative differential resistance device having negative differential resistance (NDR) under a low voltage condition using a nanowire based on an organic-inorganic hybrid halide perovskite, and a circuit thereof are provided. The quantum hybridization negative differential resistance device includes a channel formed of an organic-inorganic hybrid halide perovskite crystal and electrodes formed of its inorganic framework and is connected to opposite ends of the channel.

公开(公告)号：US10748904B2

公开(公告)日：2020-08-18

申请号：US16775808

申请日：2020-01-29

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00 ,  H01L27/108 ,  H01L29/10 ,  H01L29/08 ,  H01L27/102 ,  G11C11/4099 ,  G11C11/39 ,  H01L23/528 ,  H01L29/788 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/404 ,  H01L29/78 ,  H01L29/66 ,  H01L29/772 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/403 ,  G11C11/04 ,  G11C11/402

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

公开(公告)号：US20200075077A1

公开(公告)日：2020-03-05

申请号：US16181669

申请日：2018-11-06

申请人： Korea University Research and Business Foundation

发明人： Sang Sig KIM ,  Kyoung Ah CHO ,  Jin Sun CHO ,  Doo Hyeok LIM ,  Sol A WOO

IPC分类号： G11C11/39 ,  H01L29/08 ,  H01L29/749 ,  H01L23/528 ,  H01L29/36 ,  H01L29/49 ,  H01L29/45 ,  H01L27/105

摘要： The present disclosure discloses a feedback field-effect electronic device using a feedback loop operation and an array circuit using the feedback field-effect electronic device. According to one embodiment of the present disclosure, the array circuit includes a plurality of feedback field-effect electronic devices in which the source region of a diode structure and the drain region of an access electronic device are connected in series, wherein the diode structure is connected to a bit line and a first word line, the access electronic device is connected to a source line and a second word line, and a random access operation is performed by selectively applying voltage to the bit line and the first and second word lines.

公开(公告)号：US10553588B2

公开(公告)日：2020-02-04

申请号：US16015164

申请日：2018-06-21

申请人： TC Lab, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC分类号： G11C19/08 ,  H01L27/102 ,  H01L29/749 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L29/45 ,  H01L49/02 ,  G11C11/39 ,  H01L21/28 ,  H01L21/321 ,  H01L29/423 ,  H01L29/08

摘要： Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

公开(公告)号：US10535657B2

公开(公告)日：2020-01-14

申请号：US15683760

申请日：2017-08-22

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Valery Axelrad

IPC分类号： H01L27/102 ,  H01L21/8229 ,  H01L27/108 ,  H01L27/11512 ,  G11C15/04 ,  H01L29/66 ,  G11C11/39 ,  H01L27/08

摘要： Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

公开(公告)号：US10453847B2

公开(公告)日：2019-10-22

申请号：US16404964

申请日：2019-05-07

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00 ,  H01L27/108 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/22 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/102 ,  G11C11/39 ,  H01L23/528 ,  H01L29/788 ,  H01L29/772 ,  G11C11/4099 ,  G11C11/402 ,  G11C11/04

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

公开(公告)号：US10340276B2

公开(公告)日：2019-07-02

申请号：US16200997

申请日：2018-11-27

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： G11C14/00 ,  H01L27/108 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  G11C11/404 ,  H01L29/10 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  G11C7/22 ,  H01L29/788 ,  H01L23/528 ,  G11C11/39 ,  G11C11/4099 ,  H01L27/102 ,  H01L29/08 ,  G11C11/402 ,  G11C11/04

摘要： Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

公开(公告)号：US10283185B2

公开(公告)日：2019-05-07

申请号：US14740209

申请日：2015-06-15

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： G11C11/39 ,  G11C11/34 ,  G11C11/418 ,  G11C11/419 ,  G11C11/411 ,  G11C11/416 ,  H01L27/11 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/102 ,  H01L27/082 ,  G11C5/14

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.