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公开(公告)号：US06710664B2
公开(公告)日：2004-03-23
申请号：US10127289
申请日：2002-04-22
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03L7/087 , H03L7/10 , H03L7/1974 , H03L7/1976
摘要： The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.
摘要翻译： 本发明为分数N合成器提供了有效的粗调程序。 通常，来自合成器的锁相环（PLL）的分频参考信号和分频可控振荡器（CO）信号分别被公共因子M除以分别提供平均参考信号和平均CO信号。 分割的CO信号平均减少由CO信号的分数N除法引起的抖动。 比较平均CO信号和平均参考信号的频率，结果用于选择用于操作CO的适当调谐曲线。
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公开(公告)号：US06838951B1
公开(公告)日：2005-01-04
申请号：US10453095
申请日：2003-06-03
CPC分类号： H03L7/1976 , H03L7/113
摘要： The present invention provides circuitry for maintaining the desired phase noise across the tuning range of a frequency synthesizer by compensating the voltage controlled oscillator (VCO) bias current according to various tuning parameters available within the frequency synthesizer, thereby reducing overall current drain and inductor quality factor requirements. In general, the present invention includes a VCO bias circuit capable of controlling the VCO bias current in response to a control signal provided by additional circuitry based on the operating frequency of the frequency synthesizer. Further, the VCO bias current changes in response to changing the operating frequency of the frequency synthesizer.
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