公开(公告)号：US07818135B2

公开(公告)日：2010-10-19

申请号：US12129882

申请日：2008-05-30

申请人： Ravi Kishore Jammula ,  Andrew Wang ,  Mark Thierbach

发明人： Ravi Kishore Jammula ,  Andrew Wang ,  Mark Thierbach

IPC分类号： G06F19/00

CPC分类号： G11C29/02 ,  G06F13/1605 ,  G11C29/023 ,  G11C29/028

摘要： An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

摘要翻译： 用于定时校准外部存储器/外部设备的各个管芯之间的写入和读回数据交换的装置和方法具有主仲裁器或备选地，系统总线主机接口和外部存储器控制器之间的测试复用器，用于驱动 外部存储器/外部设备，通过测试总线主接口在主仲裁器的控制下的校准电路，为模具之间的测试数据交换提供逐步延迟的时间，并且校准电路获得指示通过或失败的通过/失败数据 测试数据交换的时间延迟。 系统总线主界面处理器系统选择对应于通过数据的校准值，并将校准值应用于各个管芯，用于在管芯之间进行写入和读回数据交换的定时。

公开(公告)号：US20090295438A1

公开(公告)日：2009-12-03

申请号：US12129882

申请日：2008-05-30

申请人： Ravi Kishore Jammula ,  Andrew Wang ,  Mark Thierbach

发明人： Ravi Kishore Jammula ,  Andrew Wang ,  Mark Thierbach

IPC分类号： H03L7/00

CPC分类号： G11C29/02 ,  G06F13/1605 ,  G11C29/023 ,  G11C29/028

摘要： An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test mux between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

摘要翻译： 用于定时校准外部存储器/外部设备的各个管芯之间的写入和读回数据交换的装置和方法具有主仲裁器或备选地，系统总线主机接口和外部存储器控制器之间的测试复用器，用于驱动 外部存储器/外部设备，通过测试总线主接口在主仲裁器的控制下的校准电路，为模具之间的测试数据交换提供逐步延迟的时间，并且校准电路获得指示通过或失败的通过/失败数据 测试数据交换的时间延迟。 系统总线主界面处理器系统选择对应于通过数据的校准值，并将校准值应用于各个管芯，用于在管芯之间进行写入和读回数据交换的定时。