公开(公告)号：US07975125B2

公开(公告)日：2011-07-05

申请号：US12476483

申请日：2009-06-02

申请人： Prasad Avss ,  Ravi Pathakola

发明人： Prasad Avss ,  Ravi Pathakola

IPC分类号： G06F12/00 ,  G06F17/50 ,  G11C8/00

CPC分类号： G11C17/08

摘要： A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

摘要翻译： ROM包括几个位输出线和X地址解码线，并存储数据集。 每个地址解码行存储唯一的数据字。 具有相同数据字的数据集中的地址由解码器映射到相同的地址解码线。 每个地址解码线电连接到由数据集确定的位输出线。 ROM的初始设计使用N个连接装置分别将N个地址解码线电连接到位输出线。 如果N超过X / 2，则进行优化处理。 优化过程涉及电连接到位输出线的每个地址解码线，并且电连接未连接到位输出线的每个地址解码线。 然后，位输出线的输出通过逻辑反相器运行，以提供正确的输出数据位。

公开(公告)号：US20090237973A1

公开(公告)日：2009-09-24

申请号：US12476483

申请日：2009-06-02

申请人： Prasad AVSS ,  Ravi Pathakola

发明人： Prasad AVSS ,  Ravi Pathakola

IPC分类号： G11C17/00 ,  G11C8/10

CPC分类号： G11C17/08

摘要： A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

摘要翻译： ROM包括几个位输出线和X地址解码线，并存储数据集。 每个地址解码行存储唯一的数据字。 具有相同数据字的数据集中的地址由解码器映射到相同的地址解码线。 每个地址解码线电连接到由数据集确定的位输出线。 ROM的初始设计使用N个连接装置分别将N个地址解码线电连接到位输出线。 如果N超过X / 2，则进行优化处理。 优化过程涉及电连接到位输出线的每个地址解码线，并且电连接未连接到位输出线的每个地址解码线。 然后，位输出线的输出通过逻辑反相器运行，以提供正确的输出数据位。