公开(公告)号：US08037440B2

公开(公告)日：2011-10-11

申请号：US12505819

申请日：2009-07-20

申请人： Prasad Avss ,  Ravi Pathakota

发明人： Prasad Avss ,  Ravi Pathakota

IPC分类号： G06F17/50 ,  G06F11/22 ,  G06F9/26 ,  G06F9/34 ,  G11C8/00

CPC分类号： G11C17/08 ,  G06F17/5045

摘要： A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

摘要翻译： 一种用于设计只读存储器（ROM）和相关设备的方法包括将数据集划分成两个或更多个子数据集，每个子​​数据集具有相同的地址空间，但是具有比原始数据集更小的位宽。 子数据集被折叠，然后提供子数据集的各自的存储单元。 存储单元的输出提供ROM的输出。 每个存储单元包括基于在行折叠期间获得的映射信息将地址映射到字线的解码器，以及由编码子数据集的数据字的解码器驱动的逻辑阵列。

公开(公告)号：US20080301410A1

公开(公告)日：2008-12-04

申请号：US11755511

申请日：2007-05-30

申请人： Prasad Avss ,  Jacob Mathews

发明人： Prasad Avss ,  Jacob Mathews

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30156

摘要： A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given instruction. Thus, the same instruction is produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. The assignment of multiple operation codes to a given instruction may occur in conjunction with the design of the processor, and dynamic selection of a particular one of those operation codes may be performed in conjunction with assembly of code for execution by the processor.

摘要翻译： 配置成对多个指令中的每一个执行多个操作代码的处理器包括耦合到存储器电路的存储器电路和处理电路。 处理电路被配置为对第一操作码进行解码以产生给定的一个指令，并且解码与第一操作码不同的第二操作码，以产生给定的指令。 因此，不管第一操作码或第二操作码是否被解码，产生用于由处理电路执行的相同指令。 多个操作代码对给定指令的分配可以与处理器的设计一起发生，并且可以结合用于处理器执行的代码的组合来执行这些操作代码中的特定一个的动态选择。

公开(公告)号：US20090282373A1

公开(公告)日：2009-11-12

申请号：US12505819

申请日：2009-07-20

申请人： Prasad Avss ,  Ravi Pathakota

发明人： Prasad Avss ,  Ravi Pathakota

IPC分类号： G06F17/50

CPC分类号： G11C17/08 ,  G06F17/5045

摘要： A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

摘要翻译： 一种用于设计只读存储器（ROM）和相关设备的方法包括将数据集划分成两个或更多个子数据集，每个子​​数据集具有相同的地址空间，但是具有比原始数据集更小的位宽。 子数据集被折叠，然后提供子数据集的各自的存储单元。 存储单元的输出提供ROM的输出。 每个存储单元包括基于在行折叠期间获得的映射信息将地址映射到字线的解码器，以及由编码子数据集的数据字的解码器驱动的逻辑阵列。

公开(公告)号：US20080104566A1

公开(公告)日：2008-05-01

申请号：US11623218

申请日：2007-01-15

申请人： Prasad AVSS ,  Ravi Pathakota

发明人： Prasad AVSS ,  Ravi Pathakota

IPC分类号： G06F17/50

CPC分类号： G11C17/08 ,  G06F17/5045

摘要： A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

摘要翻译： 一种用于设计只读存储器（ROM）和相关设备的方法包括将数据集划分成两个或更多个子数据集，每个子​​数据集具有相同的地址空间，但是具有比原始数据集更小的位宽。 子数据集被折叠，然后提供子数据集的各自的存储单元。 存储单元的输出提供ROM的输出。 每个存储单元包括基于在行折叠期间获得的映射信息将地址映射到字线的解码器，以及由编码子数据集的数据字的解码器驱动的逻辑阵列。

公开(公告)号：US07975125B2

公开(公告)日：2011-07-05

申请号：US12476483

申请日：2009-06-02

申请人： Prasad Avss ,  Ravi Pathakola

发明人： Prasad Avss ,  Ravi Pathakola

IPC分类号： G06F12/00 ,  G06F17/50 ,  G11C8/00

CPC分类号： G11C17/08

摘要： A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

摘要翻译： ROM包括几个位输出线和X地址解码线，并存储数据集。 每个地址解码行存储唯一的数据字。 具有相同数据字的数据集中的地址由解码器映射到相同的地址解码线。 每个地址解码线电连接到由数据集确定的位输出线。 ROM的初始设计使用N个连接装置分别将N个地址解码线电连接到位输出线。 如果N超过X / 2，则进行优化处理。 优化过程涉及电连接到位输出线的每个地址解码线，并且电连接未连接到位输出线的每个地址解码线。 然后，位输出线的输出通过逻辑反相器运行，以提供正确的输出数据位。

公开(公告)号：US20090237973A1

公开(公告)日：2009-09-24

申请号：US12476483

申请日：2009-06-02

申请人： Prasad AVSS ,  Ravi Pathakola

发明人： Prasad AVSS ,  Ravi Pathakola

IPC分类号： G11C17/00 ,  G11C8/10

CPC分类号： G11C17/08

摘要： A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

摘要翻译： ROM包括几个位输出线和X地址解码线，并存储数据集。 每个地址解码行存储唯一的数据字。 具有相同数据字的数据集中的地址由解码器映射到相同的地址解码线。 每个地址解码线电连接到由数据集确定的位输出线。 ROM的初始设计使用N个连接装置分别将N个地址解码线电连接到位输出线。 如果N超过X / 2，则进行优化处理。 优化过程涉及电连接到位输出线的每个地址解码线，并且电连接未连接到位输出线的每个地址解码线。 然后，位输出线的输出通过逻辑反相器运行，以提供正确的输出数据位。

公开(公告)号：US20090172069A1

公开(公告)日：2009-07-02

申请号：US11967251

申请日：2007-12-30

申请人： Prasad Avss ,  Ravi Pathakota

发明人： Prasad Avss ,  Ravi Pathakota

IPC分类号： G06F7/487

CPC分类号： G06F7/535 ,  G06F2207/5355

摘要： The invention provides a method, arithmetic divider unit, and system for dividing a dividend DZm . . . Z0 having a most significant bit and a plurality of less significant bits by a divisor having a most significant bit ZN and a plurality of less significant bits ZN−1 through Z0. The method, arithmetic divider unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN, divide the dividend DZm . . . Z0 by the first partial divisor RZN to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN−1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

摘要翻译： 本发明提供了一种分割除数DZm的方法，算术除法器单元和系统。 。 。 具有最高有效位ZN和多个较低有效位ZN-1至Z0的除数具有最高有效位和多个较低有效位的Z0。 该方法，算术除法器单元和系统绕除数到下一个有效位大于除数的最高有效位ZN以产生第一部分因子RZN，除以红利DZm。 。 。 Z0通过第一部分因子RZN产生第一部分商QN，基于从多个除数比特ZN-1到Z0中选择的一个或多个除数比特来计算一个或多个附加部分商，并且将第一部分商QN和 一个或多个额外的部分商产生估计的最终商。

公开(公告)号：US08060551B2

公开(公告)日：2011-11-15

申请号：US11967251

申请日：2007-12-30

申请人： Prasad Avss ,  Ravi Pathakota

发明人： Prasad Avss ,  Ravi Pathakota

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F2207/5355

摘要： A method, arithmetic divider unit, and system are disclosed for dividing a dividend DZM . . . Z0 having a most significant bit ZM and a plurality of less significant bits ZM−1 through Z0 by a divisor RZN . . . Z0 having a most significant bit ZN and a plurality of less significant bits ZN−1 through Z0. The method, arithmetic divisor unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN+1, divide the dividend DZM . . . Z0 by the first partial divisor RZN+1 to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN−1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

摘要翻译： 公开了一种用于划分分红DZM的方法，算术分配器单元和系统。 。 。 Z0具有最高有效位ZM和多个较低有效位ZM-1至Z0除数RZN。 。 。 Z0具有最高有效位ZN和多个较低有效位ZN-1至Z0。 该方法，算术除数单元和系数四舍五入到比除数最高有效位ZN的下一个有效位以产生第一个部分除数RZN + 1，除以除数DZM。 。 。 Z0由第一部分因子RZN + 1产生第一部分商QN，基于从多个除数比特ZN-1到Z0中选择的一个或多个除数比特计算一个或多个附加部分商，并且将第一部分商 QN和一个或多个额外的部分商产生估计的最终商。

公开(公告)号：US07623367B2

公开(公告)日：2009-11-24

申请号：US11580786

申请日：2006-10-13

申请人： Prasad Avss ,  Ravi Pathakota

发明人： Prasad Avss ,  Ravi Pathakota

IPC分类号： G11C17/00

CPC分类号： G11C17/08

摘要： A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.

摘要翻译： ROM包括几个位输出线和X地址解码线，并存储数据集。 每个地址解码行存储唯一的数据字。 具有相同数据字的数据集中的地址由解码器映射到相同的地址解码线。 每个地址解码线电连接到由数据集确定的位输出线。 ROM的初始设计使用N个连接装置分别将N个地址解码线电连接到位输出线。 如果N超过X / 2，则进行优化处理。 优化过程涉及电连接到位输出线的每个地址解码线，并且电连接未连接到位输出线的每个地址解码线。 然后，位输出线的输出通过逻辑反相器运行，以提供正确的输出数据位。

公开(公告)号：US08700886B2

公开(公告)日：2014-04-15

申请号：US11755511

申请日：2007-05-30

申请人： Prasad Avss ,  Jacob Mathews

发明人： Prasad Avss ,  Jacob Mathews

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30156

摘要： A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given instruction. Thus, the same instruction is produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. The assignment of multiple operation codes to a given instruction may occur in conjunction with the design of the processor, and dynamic selection of a particular one of those operation codes may be performed in conjunction with assembly of code for execution by the processor.

摘要翻译： 配置成对多个指令中的每一个执行多个操作代码的处理器包括耦合到存储器电路的存储器电路和处理电路。 处理电路被配置为对第一操作码进行解码以产生给定的一个指令，并且解码与第一操作码不同的第二操作码，以产生给定的指令。 因此，不管第一操作码或第二操作码是否被解码，产生用于由处理电路执行的相同指令。 多个操作代码对给定指令的分配可以与处理器的设计一起发生，并且这些操作代码中的特定一个操作代码的动态选择可以结合用于由处理器执行的代码的组合来执行。