公开(公告)号：US20100250980A1

公开(公告)日：2010-09-30

申请号：US12413713

申请日：2009-03-30

申请人： Chao Chun Wang ,  Yung-Sheng Chiu ,  Ren-Yu Yu

发明人： Chao Chun Wang ,  Yung-Sheng Chiu ,  Ren-Yu Yu

IPC分类号： G06F1/32 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

摘要： A method for reducing power consumption of a device with an embedded memory module is provided. The device includes comprises a processor, an embedded memory module, a software module, a power supplying unit, and an auxiliary logic. The embedded memory module is accessed by the processor and partitioned into a plurality of memory blocks in accordance with a first predetermined rule. The software module comprises an instruction set and a data set. The software module is segmented into a plurality of segments in accordance with a second predetermined rule. The power supplying unit provides power to the plurality of memory blocks. The auxiliary logic controls the power supplying unit. The power supplied to a memory block is switched on or off in accordance with a condition.

摘要翻译： 提供了一种用于降低具有嵌入式存储器模块的设备的功耗的方法。 该设备包括处理器，嵌入式存储器模块，软件模块，供电单元和辅助逻辑。 嵌入式存储器模块由处理器访问，并且根据第一预定规则被划分成多个存储器块。 软件模块包括指令集和数据集。 根据第二预定规则，软件模块被分段成多个段。 供电单元向多个存储块供电。 辅助逻辑控制供电单元。 提供给存储器块的电源根据条件被打开或关闭。

公开(公告)号：US08127167B2

公开(公告)日：2012-02-28

申请号：US12413713

申请日：2009-03-30

申请人： Chao Chun Wang ,  Yung-Sheng Chiu ,  Ren-Yu Yu

发明人： Chao Chun Wang ,  Yung-Sheng Chiu ,  Ren-Yu Yu

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

摘要： A method for reducing power consumption of a device with an embedded memory module is provided. The device includes comprises a processor, an embedded memory module, a software module, a power supplying unit, and an auxiliary logic. The embedded memory module is accessed by the processor and partitioned into a plurality of memory blocks in accordance with a first predetermined rule. The software module comprises an instruction set and a data set. The software module is segmented into a plurality of segments in accordance with a second predetermined rule. The power supplying unit provides power to the plurality of memory blocks. The auxiliary logic controls the power supplying unit. The power supplied to a memory block is switched on or off in accordance with a condition.

摘要翻译： 提供了一种用于降低具有嵌入式存储器模块的设备的功耗的方法。 该设备包括处理器，嵌入式存储器模块，软件模块，供电单元和辅助逻辑。 嵌入式存储器模块由处理器访问，并且根据第一预定规则被划分成多个存储器块。 软件模块包括指令集和数据集。 根据第二预定规则，软件模块被分段成多个段。 供电单元向多个存储块供电。 辅助逻辑控制供电单元。 提供给存储器块的电源根据条件被打开或关闭。