公开(公告)号：US5627492A

公开(公告)日：1997-05-06

申请号：US552709

申请日：1995-11-03

Applicant: Mark Weaver ,  Robert D. Berger ,  Dwight D. Esgar

Inventor： Mark Weaver ,  Robert D. Berger ,  Dwight D. Esgar

IPC: H03K19/00 ,  G05F1/10

CPC classification number: H03K19/0008

Abstract: An integrated circuit is divided into functional blocks. The integrated circuit includes current source based circuitry such as Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled Logic (SCL) Isolation blocks (14-20) are placed in signal paths to and from each functional block. A multiple output bias driver circuit (13) couples to each functional block. The multiple output bias driver circuit (13) provides a signal for enabling and disabling current sources of a functional block. A bias control logic circuit (12) controls the isolation blocks (14-20) and the multiple output bias driver (13). A functional block that is idle in the operation of the integrated circuit is shut down by the bias control logic circuit (12) to conserve power. The multiple output bias driver circuit (13) receives control signals from the bias control logic circuit (12) to turn off current sources in the idle functional block. Isolation blocks (14-20) receive control signals from the bias control logic circuit (12) to isolate the idle functional block and to provide a predetermined logic level in the signal paths from the idle functional to prevent propagation of an erroneous signal.

Abstract translation: 集成电路分为功能块。 集成电路包括基于电流源的电路，例如发射极耦合逻辑（ECL），电流模式逻辑（CML）或源耦合逻辑（SCL）隔离块（14-20）放置在到每个功能块的信号路径中。 多输出偏置驱动器电路（13）耦合到每个功能块。 多输出偏置驱动器电路（13）提供用于启用和禁用功能块的电流源的信号。 偏置控制逻辑电路（12）控制隔离块（14-20）和多输出偏置驱动器（13）。 在集成电路的操作中空闲的功能块被偏置控制逻辑电路（12）关断以节省功率。 多输出偏置驱动器电路（13）从偏置控制逻辑电路（12）接收控制信号以关闭空闲功能块中的电流源。 隔离块（14-20）接收来自偏置控制逻辑电路（12）的控制信号以隔离空闲功能块并且提供来自空闲功能的信号路径中的预定逻辑电平以防止错误信号的传播。

公开(公告)号：US5001370A

公开(公告)日：1991-03-19

申请号：US547257

申请日：1990-07-02

Applicant: M. Nghiem Phan ,  Robert D. Berger

Inventor： M. Nghiem Phan ,  Robert D. Berger

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/013 ,  H03K19/018

CPC classification number: H03K19/00376 ,  H03K19/001 ,  H03K19/013 ,  H03K19/01812

Abstract: A high speed voltage translator is responsive to an ECL input signal for providing a TTL output signal at an output while clamping the low output voltage thereof to a predetermined value. The ECL input signal is converted to first and second complementary control signals for driving the upper and lower transistors in the output stage, respectively. The second control signal enables a third transistor, the base of which is connected via a serial diode and resistor combination to a second collector of the lower transistor in the output stage. The base-emitter junction potential of the third transistor cancels the potential across the diode whereby the collector of the lower transistor that is the output of the voltage translator is clamped at one base-emitter junction potential less the voltage across the resistor. Furthermore, the current flowing through the resistor is compensated for temperature variation whereby the low output voltage is independent of temperature. The first and second control signals enable separate charge and discharge paths for the upper and lower transistors whereby the associated propagation delays may be controlled so as to inhibit simultaneous conduction through the output stage.

Abstract translation: 高速电压转换器响应于ECL输入信号，用于在输出端提供TTL输出信号，同时将其低输出电压钳位到预定值。 ECL输入信号被转换为第一和第二互补控制信号，用于分别驱动输出级中的上和下晶体管。 第二控制信号使得第三晶体管的基极通过串联二极管和电阻器组合连接到输出级中的下晶体管的第二集电极。 第三晶体管的基极 - 发射极结电位消除了二极管两端的电位，因此作为电压转换器输出的下部晶体管的集电极被钳位在一个基极 - 发射极结电位上，减小了电阻两端的电压。 此外，流经电阻器的电流被补偿温度变化，由此低输出电压与温度无关。 第一和第二控制信号为上和下晶体管提供分开的充电和放电路径，由此可以控制相关联的传播延迟，以便抑制通过输出级的同时传导。