公开(公告)号：US07261982B2

公开(公告)日：2007-08-28

申请号：US10736295

申请日：2003-12-15

申请人： Barthelemy Fondeur ,  Anca L. Sala ,  Robert J. Brainard ,  David K. Nakamoto ,  Tom Truong ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan

发明人： Barthelemy Fondeur ,  Anca L. Sala ,  Robert J. Brainard ,  David K. Nakamoto ,  Tom Truong ,  Sanjay M. Thekdi ,  Anantharaman Vaidyanathan

IPC分类号： G03F1/00 ,  G03C5/00

CPC分类号： G03F7/70466 ,  G03F1/50 ,  G03F1/70

摘要： The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.

摘要翻译： 本申请涉及使用光刻掩模组，光刻掩模组以及用光刻掩模组制造的平面电路制造平面电路的方法。 本发明涉及将光刻掩模分为两部分，即主掩模和一个或多个从属掩模。 主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。 特别地，主掩模用作模板以提供用于平面电路的总体布局，而每个从屏蔽被改变以调谐和/或定制平面电路。 由于只有一小部分平面电路被重新设计和/或重写为新的掩模（即，从属掩模），本发明提供了一种用于优化平面电路的简单且成本有效的方法。 此外，由于大多数掩模错误将源自主掩模，本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。

公开(公告)号：US20090263142A1

公开(公告)日：2009-10-22

申请号：US12390056

申请日：2009-02-20

申请人： Jinxi Shen ,  Jyoti K. Bhardwaj ,  Barthelemy Fondeur ,  Douglas E. Crafts ,  Robert J. Brainard ,  Boping Xie ,  David J. Chapman

发明人： Jinxi Shen ,  Jyoti K. Bhardwaj ,  Barthelemy Fondeur ,  Douglas E. Crafts ,  Robert J. Brainard ,  Boping Xie ,  David J. Chapman

IPC分类号： H04B10/00

CPC分类号： G02F1/225 ,  G02B6/12007 ,  G02B6/4201 ,  G02F2201/16 ,  G02F2203/055

摘要： A tunable PLC optical filter having sequentially connected thermally tunable Mach-Zehnder (MZ) interferometers is described. The MZ interferometers, having free spectral ranges matching ITU frequency grid spacing, are tuned so as to have a common passband centered on the frequency of the signal being selected, while having at least one of the stopbands centered on any other ITU frequency. Any other optical channel that may be present at any other ITU frequency is suppressed as a result. The PLC chip, including a zero-dispersion lattice-filter interleaver stage, a switchable fine-resolution stage and, or a retroreflector for double passing the filter, is packaged into a hot-pluggable XFP transceiver package. A compensation heater is used to keep constant the amount of heat applied to the PLC chip inside the XFP package, so as to lessen temperature variations upon tuning of the PLC optical filter.

摘要翻译： 描述了具有顺序连接的可热调谐的马赫 - 曾德（MZ）干涉仪的可调谐PLC光学滤波器。 具有与ITU频率格栅间隔相匹配的自由频谱范围的MZ干涉仪被调谐，以具有以所选信号的频率为中心的公共通带，同时具有以任何其它ITU频率为中心的至少一个阻带。 因此可能会抑制任何其他ITU频率出现的任何其他光信道。 包括零色散格子滤波器交错器级，可切换精细分辨率级和用于双通过滤波器的后向反射器的PLC芯片被封装成可热插拔的XFP收发器封装。 使用补偿加热器来保持施加到XFP封装内的PLC芯片的热量，以便在调节PLC滤光器时降低温度变化。

公开(公告)号：USD404736S

公开(公告)日：1999-01-26

申请号：US82569

申请日：1998-01-26

申请人： Jason Joel Alvarez ,  Robert J. Brainard

设计人： Jason Joel Alvarez ,  Robert J. Brainard

公开(公告)号：US08340523B2

公开(公告)日：2012-12-25

申请号：US12390056

申请日：2009-02-20

申请人： Jinxi Shen ,  Jyoti K. Bhardwaj ,  Barthelemy Fondeur ,  Douglas E. Crafts ,  Robert J. Brainard ,  Boping Xie ,  David J. Chapman

发明人： Jinxi Shen ,  Jyoti K. Bhardwaj ,  Barthelemy Fondeur ,  Douglas E. Crafts ,  Robert J. Brainard ,  Boping Xie ,  David J. Chapman

IPC分类号： H04J14/02

CPC分类号： G02F1/225 ,  G02B6/12007 ,  G02B6/4201 ,  G02F2201/16 ,  G02F2203/055

摘要： A tunable PLC optical filter having sequentially connected thermally tunable Mach-Zehnder (MZ) interferometers is described. The MZ interferometers, having free spectral ranges matching ITU frequency grid spacing, are tuned so as to have a common passband centered on the frequency of the signal being selected, while having at least one of the stopbands centered on any other ITU frequency. Any other optical channel that may be present at any other ITU frequency is suppressed as a result. The PLC chip, including a zero-dispersion lattice-filter interleaver stage, a switchable fine-resolution stage and, or a retroreflector for double passing the filter, is packaged into a hot-pluggable XFP transceiver package. A compensation heater is used to keep constant the amount of heat applied to the PLC chip inside the XFP package, so as to lessen temperature variations upon tuning of the PLC optical filter.

摘要翻译： 描述了具有顺序连接的可热调谐的马赫 - 曾德（MZ）干涉仪的可调谐PLC光学滤波器。 具有与ITU频率格栅间隔相匹配的自由频谱范围的MZ干涉仪被调谐，以具有以所选信号的频率为中心的公共通带，同时具有以任何其它ITU频率为中心的至少一个阻带。 因此可能会抑制任何其他ITU频率出现的任何其他光信道。 包括零色散格子滤波器交错器级，可切换精细分辨率级和用于双通过滤波器的后向反射器的PLC芯片被封装成可热插拔的XFP收发器封装。 使用补偿加热器来保持施加到XFP封装内的PLC芯片的热量，以便在调节PLC滤光器时降低温度变化。

公开(公告)号：US07162108B2

公开(公告)日：2007-01-09

申请号：US11015223

申请日：2004-12-17

申请人： Anca L. Sala ,  Duncan W. Harwood ,  Barthelemy Fondeur ,  Anantharaman Vaidyanathan ,  Robert J. Brainard ,  Sanjay M. Thekdi ,  Thomas T. Nguyen ,  Ian Hutagalung

发明人： Anca L. Sala ,  Duncan W. Harwood ,  Barthelemy Fondeur ,  Anantharaman Vaidyanathan ,  Robert J. Brainard ,  Sanjay M. Thekdi ,  Thomas T. Nguyen ,  Ian Hutagalung

IPC分类号： G02F1/01 ,  G02F1/035 ,  G02F1/00 ,  G02B26/00 ,  G02B6/26 ,  G02B6/42

CPC分类号： G02F1/0147 ,  G02B6/12007 ,  G02B6/266 ,  G02F1/21 ,  G02F2001/0113 ,  G02F2001/212 ,  G02F2203/06

摘要： The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all. Segmented trenches appear to allow for the lowest stress on the two waveguide arms of all the cases including no trench and trenched devices.

摘要翻译： 本发明涉及一种构成马赫曾德平面光波回路的可变光衰减器，特别是包括用于隔热和应力释放的通道波导支撑结构，以减少器件中的偏振相关损耗（PDL）和功耗。 功率减小沟槽包括在蚀刻工艺中在它们之间具有小的应力消除柱的包层材料的纵向段。 MZI的波导由主柱结构和消除沟槽后保留的积分应力消除柱支撑。 波导三面被空气包围，以改善热隔离。 与现有技术的连续沟槽设计相比，本发明的性能显示出PDL和消光比的显着改善，并且在更少的程度上，在完全不使用功率降低沟槽的情况下。 分段沟槽似乎允许在所有情况下的两个波导臂上的最小应力，包括没有沟槽和沟槽的器件。

公开(公告)号：USD442938S1

公开(公告)日：2001-05-29

申请号：US29117781

申请日：2000-01-21

申请人： Jack Brian Hough ,  Robert J. Brainard

设计人： Jack Brian Hough ,  Robert J. Brainard

公开(公告)号：US20080292239A1

公开(公告)日：2008-11-27

申请号：US12126176

申请日：2008-05-23

申请人： Barthelemy Fondeur ,  Edmond J. Murphy ,  Robert J. Brainard

发明人： Barthelemy Fondeur ,  Edmond J. Murphy ,  Robert J. Brainard

IPC分类号： G02B6/12

CPC分类号： G02B6/12014 ,  G02B6/12011

摘要： The invention relates to waveguiding structures in planar lightwave circuit devices that include a transition region between a slab waveguide and channel waveguides to reduce optical coupling loss. In particular star couplers and arrayed waveguide gratings incorporating the transition region of the present invention demonstrate reduced insertion loss. By creating a transition region composed of transverse rows intersecting the output waveguide array, where the rows have equal dimensions and the effective refractive index is controlled by increasing the spacing width gradually from row to row, an adiabatic transition is created from slab waveguide to channel waveguide array. This structure provides low insertion loss within practical manufacturing tolerances. In addition, the present invention has found that by incorporating the transition region of the present invention into an AWG, the reduced insertion loss can be controlled as uniform insertion loss across the channels.

摘要翻译： 本发明涉及平面光波电路器件中的波导结构，其包括在平板波导和沟道波导之间的过渡区域以减少光耦合损耗。 特别地，结合本发明的过渡区域的星形耦合器和阵列波导光栅显示出降低的插入损耗。 通过产生由与输出波导阵列交叉的横向行组成的过渡区域，其中行具有相等的尺寸，并且通过逐行增加间隔宽度来控制有效折射率，从平板波导到通道波导产生绝热转变 数组。 该结构在实际制造公差内提供低插入损耗。 此外，本发明已经发现，通过将本发明的过渡区域结合到AWG中，可以将减小的插入损耗控制为在通道上均匀的插入损耗。

公开(公告)号：US4903199A

公开(公告)日：1990-02-20

申请号：US183195

申请日：1988-04-19

申请人： W. Russ Keenan ,  Stephen F. Comen ,  Robert J. Brainard

发明人： W. Russ Keenan ,  Stephen F. Comen ,  Robert J. Brainard

IPC分类号： G01R31/316 ,  G01R31/319

CPC分类号： G01R31/316 ,  G01R31/31903 ,  G06F2201/865

摘要： Disclosed is a method which speeds up interpretive test program code execution and allows rapid changes to the test code. The tester utilized with the present invention uses the interpretive language TPL (Test Program Language) for device test programs. The present invention uses the first execution of a statement in an interpreted environment to build a table of address value pairs corresponding to the values computed by the statement. It then changes the pseudo code of the statement to use a short assembly language routine to write the values in the table fo their appropriate addresses, using the memory mapped features of the test head hardware. This is done by translating each TPL line into pseudo code as it is loaded. The first time a line of code is executed, it builds a table which contains all the values computed and the addresses to which they are written. The next time the statement is executed, the verb pointer points to the turbo software which is executed rather than the TPL statement. Since the test head hardware is memory mapped, no distinction needs to be made between data being saved by the software and data being written to the test head. All error checking and calibration is done by the emulator code the first time the statement is executed and does not need to be repeated thereafter.

摘要翻译： 公开了一种加速解释性测试程序代码执行并允许快速更改测试代码的方法。 本发明使用的测试仪使用解释语言TPL（测试程序语言）进行设备测试程序。 本发明使用在解释环境中的语句的第一次执行来构建对应于由语句计算的值的地址值对的表。 然后，将该语句的伪代码更改为使用简短的汇编语言例程，使用测试头硬件的内存映射功能将表中的值写入其适当的地址。 这是通过在加载时将每个TPL行转换为伪代码来完成的。 第一次执行一行代码时，它会构建一个包含所有计算值和写入地址的表。 下一次执行该语句时，动词指针指向被执行的turbo软件，而不是TPL语句。 由于测试头硬件是存储器映射的，所以不需要区分软件保存的数据和写入测试头的数据。 所有错误检查和校准都是在第一次执行语句时由仿真器代码完成的，之后不需要重复。