-
公开(公告)号：US08566764B2
公开(公告)日：2013-10-22
申请号：US12771404
申请日：2010-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.
摘要翻译： 提供了一种机制，用于通过在包括存储器阵列的逻辑模型上使用相位抽象来增加基于变换的形式验证解决方案的可扩展性。 该机制操纵阵列以创建其读取和写入端口的多个副本，表示不同的模数时间帧。 该机制将所有写入前读数组转换为预写入，并将数组周围的旁路路径从写入端口读入端口，以捕获任何必需的并行读写转发。 该机制使用一组额外的旁路路径来确保通过展开固有的相位抽象将有效并发的正确写入数据转发到正确的读取端口。 如果给定的读取端口被禁用或获取超出范围的数据，则该机制将随机数据应用于读取端口数据输出。
-
2.发明授权公开(公告)号：US08336016B2
公开(公告)日：2012-12-18
申请号：US12775622
申请日：2010-05-07
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided in a design environment for eliminating, coalescing, or bypassing ports. The design environment comprises one mechanism to eliminate unnecessary ports in arrays using disabled and disconnected pin information. The design environment may comprise another mechanism to combine and reduce the number of array ports using address comparisons. The design environment may comprise another mechanism to combine and reduce the number of array ports using disjoint enable comparisons. The design environment may comprise one mechanism to combine and reduce the number of array ports using “don't care” computations. The design environment may comprise another mechanism to reduce the number of array ports through bypassing write-to-read paths around arrays.
摘要翻译： 在用于消除，聚结或绕过端口的设计环境中提供了机制。 设计环境包括使用禁用和断开的引脚信息消除阵列中不必要的端口的一种机制。 设计环境可以包括使用地址比较来组合和减少阵列端口的数量的另一种机制。 设计环境可以包括使用不相交使能比较来组合和减少阵列端口的数量的另一种机制。 设计环境可以包括一种机制，可以使用不关心计算来组合和减少阵列端口的数量。 设计环境可以包括通过绕过阵列周围的写入读取路径来减少阵列端口的数量的另一种机制。
-
公开(公告)号：US08327302B2
公开(公告)日：2012-12-04
申请号：US12580330
申请日：2009-10-16
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译： 用于执行逻辑设计分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。 还确定了初始瞬态行为的持续时间。 基于初始瞬态行为收集关于逻辑设计的减少信息。 然后基于减少信息来修改网表。
-
4.发明申请公开(公告)号：US20120271792A1
公开(公告)日：2012-10-25
申请号：US13458252
申请日：2012-04-27
IPC分类号： G06N5/00
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that arc determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译： 提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。 确定SAT问题是否满足约束列表中的约束。 响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。 对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。 响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。
-
公开(公告)号：US20120271786A1
公开(公告)日：2012-10-25
申请号：US13092262
申请日：2011-04-22
IPC分类号： G06N5/02
CPC分类号： G06F17/504 , G06F17/11 , G06F2217/06
摘要： A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.
摘要翻译： 提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。 确定SAT问题是否满足约束列表中的约束。 响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。 对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。 响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。
-
公开(公告)号：US08171437B2
公开(公告)日：2012-05-01
申请号：US12410968
申请日：2009-03-25
IPC分类号： G06F9/45
CPC分类号： G06F17/5022
摘要： A method, system and computer program product for X-Saturated ternary simulation based reduction. An X-Saturated ternary simulation (XSTS) utility, which executes on a computer system, receives design information, where the design information includes a netlist. The XSTS utility initializes one or more data structures and/or variables and simulates, in a ternary fashion, the netlist at a time value by applying logical X values to all RANDOM gates of the netlist and to registers marked X_SATURATED. For each register of the netlist XSTS utility: determines whether or not the register departs from its expected prefix behavior, and if the register departs from its expected prefix behavior, the register is marked as X_SATURATED and the current state is updated with an X value upon the register. XSTS utility can store the current state in a data structure and can use the information from the data structure to simplify the design.
摘要翻译： 一种用于X饱和三元模拟减少的方法，系统和计算机程序产品。 在计算机系统上执行的X饱和三元模拟（XSTS）实用程序接收设计信息，其中设计信息包括网表。 XSTS实用程序初始化一个或多个数据结构和/或变量，并通过将网络表的所有RANDOM门应用逻辑X值和标记为X_SATURATED的寄存器以三元方式模拟网表。 对于网表XSTS实用程序的每个寄存器：确定寄存器是否偏离其预期的前缀行为，并且如果寄存器偏离其预期的前缀行为，则该寄存器被标记为X_SATURATED，并且当前状态被更新为X值 登记册。 XSTS实用程序可以将当前状态存储在数据结构中，并可以使用数据结构中的信息来简化设计。
-
7.发明申请Techniques for Employing Retiming and Transient Simplification on Netlists That Include Memory Arrays 失效对包含内存数组的网络表进行重定时和瞬态简化的技术公开(公告)号：US20120054702A1
公开(公告)日：2012-03-01
申请号：US12872490
申请日：2010-08-31
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.
摘要翻译： 用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。 该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。 然后基于减少信息来修改网表。
-
公开(公告)号：US20110276932A1
公开(公告)日：2011-11-10
申请号：US12775633
申请日：2010-05-07
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays.
摘要翻译： 在用于数组连接的设计环境中提供了机制。 设计环境包括将阵列与启用和地址兼容的端口连接起来的一种机制，从而减少网表中的阵列数量。 设计环境包括基于兼容的使能，地址和数据兼容的写入端口将读取端口从一个阵列迁移到另一个阵列的另一种机制，从而减少网表中的阵列数量。 设计环境还包括消除不必要的阵列的另一种机制。
-
公开(公告)号：US20110271244A1
公开(公告)日：2011-11-03
申请号：US12771613
申请日：2010-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition which enables optimal reductions though input reparameterization given a netlist with constraints. A post-processing mechanism next prevents input reparameterization from creating topologically inconsistent models in the presence of arrays. Additionally, this technique may be used to rectify inconsistent topologies that may arise when reparameterizing even netlists without arrays, namely false sequential dependencies across initialization constructs. Furthermore, a mechanism is provided to undo the effects of memory array based input reparameterization on verification results.
摘要翻译： 提供了一种机制，用于通过在包括存储器阵列的逻辑模型上使用输入重新参数化来增加形式验证解决方案的可扩展性。 预处理机制使得能够选择基于切割的设计分区，其允许通过给定具有约束的网表的输入重新参数化来实现最佳减少。 接下来的后处理机制可以防止输入重新参数化在数组存在的情况下创建拓扑不一致的模型。 另外，这种技术可以被用来纠正在没有数组的情况下再次参数化网格表时可能出现的不一致的拓扑，即跨初始化结构的错误的顺序依赖。 此外，提供了一种机制来消除基于存储器阵列的输入重新参数化对验证结果的影响。
-
公开(公告)号：US20110271243A1
公开(公告)日：2011-11-03
申请号：US12771404
申请日：2010-04-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.
摘要翻译： 提供了一种机制，用于通过在包括存储器阵列的逻辑模型上使用相位抽象来增加基于变换的形式验证解决方案的可扩展性。 该机制操纵阵列以创建其读取和写入端口的多个副本，表示不同的模数时间帧。 该机制将所有写入前读数组转换为预写入，并将数组周围的旁路路径从写入端口读入端口，以捕获任何必需的并行读写转发。 该机制使用一组额外的旁路路径来确保通过展开固有的相位抽象将有效并发的正确写入数据转发到正确的读取端口。 如果给定的读取端口被禁用或获取超出范围的数据，则该机制将随机数据应用于读取端口数据输出。
-
-
-
-
-
-
-
-
-
搜索结果
46 条记录 (耗时 0.038 秒)
