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19 条记录 (耗时 0.037 秒)

    Testing address lines of a memory controller
    2.
    发明授权
    Testing address lines of a memory controller 有权

    公开(公告)号：US07085973B1

    公开(公告)日：2006-08-01

    申请号：US10192376

    申请日：2002-07-09

    申请人： Robert Yin

    发明人： Robert Yin

    IPC分类号： G11C29/00

    CPC分类号： G11C29/02 ,  G11C29/025

    摘要： All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.

    Network media access controller embedded in an integrated circuit host interface
    3.
    发明授权
    Network media access controller embedded in an integrated circuit host interface 有权
    网络媒体访问控制器嵌入在集成电路主机接口中

    公开(公告)号：US07761643B1

    公开(公告)日：2010-07-20

    申请号：US12352225

    申请日：2009-01-12

    申请人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant ,  Stuart A. Nisbet ,  Gareth D. Edwards

    发明人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant ,  Stuart A. Nisbet ,  Gareth D. Edwards

    IPC分类号： G06F13/00 ,  G06F9/26 ,  H04L12/00

    CPC分类号： G06F15/7867

    摘要： A media access controller system embedded in an integrated circuit is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in an integrated circuit. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

    摘要翻译： 描述嵌入在集成电路中的媒体访问控制器系统。 用于与第一处理器进行通信的平台相关桥接器，其中所述平台相关桥接器与所述第一处理器的平台相关联，并且所述第一处理器嵌入在集成电路中。 主机接口电路耦合到与平台相关的桥接器，并且被配置为提供处理器接口，其中处理器接口用于经由平台相关桥接器与第一处理器通信，并且处理器接口具有平台独立总线，用于与第二 处理器。 至少一个媒体访问控制器耦合到主机接口电路。

    Network media access controller embedded in a programmable logic device-address filter
    6.
    发明授权
    Network media access controller embedded in a programmable logic device-address filter 有权
    嵌入在可编程逻辑器件地址过滤器中的网络介质访问控制器

    公开(公告)号：US07143218B1

    公开(公告)日：2006-11-28

    申请号：US11040135

    申请日：2005-01-21

    申请人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant

    发明人： Robert Yin ,  Hamish T. Fallside ,  Richard P. Burnley ,  Nicholas McKay ,  Martin B. Rhodes ,  Douglas M. Grant

    IPC分类号： G06F13/14 ,  H04L12/28

    CPC分类号： G06F15/7867

    摘要： Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block) located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

    摘要翻译： 描述了用于媒体访问控制器的地址过滤的方法和装置。 位于可编程逻辑器件中的专用集成电路块包括媒体访问控制器。 媒体访问控制器包括地址过滤器，其包括：地址过滤器模块，耦合到每个地址过滤器模块的第一逻辑树，并且被配置为提供用于在丢弃的帧和地址过滤的帧之间进行描绘的帧丢弃信号; 以及耦合到每个地址过滤器模块以提供地址有效信号的第二逻辑树。

    Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
    7.
    发明授权
    Method and system for controlling default values of flip-flops in PGA/ASIC-based designs 有权
    用于控制PGA / ASIC设计中触发器默认值的方法和系统

    公开(公告)号：US06976160B1

    公开(公告)日：2005-12-13

    申请号：US10082630

    申请日：2002-02-22

    申请人： Robert Yin ,  Mehul R. Vashi

    发明人： Robert Yin ,  Mehul R. Vashi

    IPC分类号： G06F1/24 ,  H03K19/177

    CPC分类号： H03K19/17772 ,  G06F1/24

    摘要： During a reset condition or prior to system initialization of an FPGA-based system (100), a FPGA (102) can be pre-configured by loading a value from a memory cell (108) into at least one flip-flop (312) of the FPGA, which represents a configuration register for an FPGA memory controller (106). The FPGA memory controller can be configured using the value loaded in the flip-flop. The value loaded into the flip-flop from the memory cell can be a default value previously stored in the memory cell.

    摘要翻译： 在复位条件期间或在基于FPGA的系统（100）的系统初始化之前，可以通过将来自存储器单元（108）的值加载到至少一个触发器（312）中来预先配置FPGA（102） 的FPGA，其表示用于FPGA存储器控制器（106）的配置寄存器。 可以使用触发器中加载的值来配置FPGA存储器控制器。 从存储器单元加载到触发器的值可以是先前存储在存储器单元中的默认值。

    Network media access controller embedded in a programmable logic device—host interface control generator
    8.
    发明授权
    Network media access controller embedded in a programmable logic device—host interface control generator 有权
    网络媒体接入控制器嵌入可编程逻辑器件 - 主机接口控制发生器

    公开(公告)号：US07376774B1

    公开(公告)日：2008-05-20

    申请号：US11040136

    申请日：2005-01-21

    申请人： Robert Yin ,  Richard P. Burnley

    发明人： Robert Yin ,  Richard P. Burnley

    IPC分类号： G06F13/00 ,  G06F12/10

    CPC分类号： H04L12/56 ,  H04J3/0697 ,  H04L45/60

    摘要： Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

    摘要翻译： 描述了用于媒体访问控制器的地址过滤的方法和装置。 位于可编程逻辑器件中的专用集成电路块包括媒体访问控制器。 媒体访问控制器包括地址过滤器，其包括：地址过滤器模块，耦合到每个地址过滤器模块的第一逻辑树，并且被配置为提供用于在丢弃的帧和地址过滤的帧之间进行描绘的帧丢弃信号; 以及耦合到每个地址过滤器模块以提供地址有效信号的第二逻辑树。

    Processor block placement relative to memory in a programmable logic device
    9.
    发明授权
    Processor block placement relative to memory in a programmable logic device 有权
    相对于可编程逻辑器件中的存储器的处理器块放置

    公开(公告)号：US07315918B1

    公开(公告)日：2008-01-01

    申请号：US11035776

    申请日：2005-01-14

    申请人： Robert Yin

    发明人： Robert Yin

    IPC分类号： G06F12/00

    CPC分类号： G06F15/7857

    摘要： A programmable logic device having groups of data and instruction memory blocks separated by a processor block is described. The processor block including an embedded processor and data and instruction memory controllers. The data and instruction memory blocks respectively including data and memory groupings of block random access memories.

    摘要翻译： 描述了具有由处理器块分隔的数据组和指令存储器块的可编程逻辑器件。 处理器块包括嵌入式处理器和数据和指令存储器控制器。 数据和指令存储器块分别包括块随机存取存储器的数据和存储器分组。

    Method and apparatus for controlling an operating mode for an embedded Ethernet media access controller
    10.
    发明授权
    Method and apparatus for controlling an operating mode for an embedded Ethernet media access controller 有权
    用于控制嵌入式以太网媒体接入控制器的操作模式的方法和装置

    公开(公告)号：US08284801B1

    公开(公告)日：2012-10-09

    申请号：US12693988

    申请日：2010-01-26

    申请人： Mehulkumar R. Vashi ,  Robert Yin ,  Jayant Mittal ,  Nicholas McKay ,  Julian Kain ,  Martin B. Rhodes ,  Mark R. Nethercot

    发明人： Mehulkumar R. Vashi ,  Robert Yin ,  Jayant Mittal ,  Nicholas McKay ,  Julian Kain ,  Martin B. Rhodes ,  Mark R. Nethercot

    IPC分类号： H04J3/16

    CPC分类号： H04L43/0817 ,  G06F2221/2105

    摘要： Method and apparatus for controlling an operating mode of an Ethernet media access controller (MAC) embedded in a programmable device is described. In some examples, a configuration circuit is configured to receive a configuration signal from configuration memory of the programmable device and a host signal from a host bus of the programmable device, and configured to output a control length check disable signal the value of which depends on the value of at least one of the configuration signal or the host signal. A parameter check circuit is configured to receive a control signal derived from at least one of the control length check disable signal or the configuration signal, and configured to selectively disable checking a length of each control frame in frames received by the Ethernet MAC based on a value of the control signal.

    摘要翻译： 描述了用于控制嵌入在可编程设备中的以太网介质访问控制器（MAC）的操作模式的方法和装置。 在一些示例中，配置电路被配置为从可编程设备的配置存储器接收配置信号和来自可编程设备的主机总线的主机信号，并且被配置为输出其值取决于的控制长度检查禁用信号 配置信号或主机信号中的至少一个的值。 参数检查电路被配置为接收从控制长度检查禁止信号或配置信号中的至少一个导出的控制信号，并且被配置为选择性地禁止基于以太网MAC接收的帧中的每个控制帧的长度 控制信号的值。