公开(公告)号：US08522126B1

公开(公告)日：2013-08-27

申请号：US12977011

申请日：2010-12-22

申请人： Zheng Chen ,  Rohith Sood ,  Loren McLaury

发明人： Zheng Chen ,  Rohith Sood ,  Loren McLaury

IPC分类号： G06F11/10

CPC分类号： G06F11/004

摘要： A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM rows, and wherein a subset of the columns in each RAM row are RAM columns and at least one column in each RAM row is a flag bit column, the memory cells corresponding to the flag bit column and RAM rows operable to store flag bit signals; a soft error detection (SED) circuit operable to read the configuration memory to derive a checksum; a logic circuit to determine if a RAM row is being read by the SED circuit that includes an asserted flag bit; and a blocking circuit that provides a known logical value to the SED circuit responsive to the logic circuit to block readback of the memory cells corresponding to the RAM rows and RAM columns.

摘要翻译： 提供了一种可编程逻辑器件（PLD），其包括：配置存储器，包括根据行和列排列的多个存储器单元，其中行的子集是RAM行，并且其中每个RAM行中的列的子集是 RAM列和每个RAM行中的至少一列是标志位列，对应于标志位列的存储器单元和可用于存储标志位信号的RAM行; 软错误检测（SED）电路，用于读取配置存储器以得到校验和; 逻辑电路，用于确定由SED电路读取的RAM行是否包括一个断言的标志位; 以及阻塞电路，其响应于逻辑电路向SED电路提供已知的逻辑值，以阻止对应于RAM行和RAM列的存储单元的读回。

公开(公告)号：US08477549B1

公开(公告)日：2013-07-02

申请号：US12976520

申请日：2010-12-22

申请人： Rohith Sood ,  Zheng Chen ,  Loren McLaury

发明人： Rohith Sood ,  Zheng Chen ,  Loren McLaury

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  H03K19/17744 ,  H03K19/17792

摘要： Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a programmable logic device (PLD) includes a plurality of static random access memory (SRAM) cells adapted to configure the PLD for an intended use. A pair of bitlines are connected to the SRAM cells. At least one of the SRAM cells is adapted to provide data signals to the bitlines in response to a wordline signal received by the one of the SRAM cells during a read operation. A sense amplifier is connected to the bitlines and adapted to detect a data value from the data signals in response to a trigger signal received by the sense amplifier during the read operation. Logic is adapted to delay the trigger signal relative to the wordline signal to permit the data signals to settle before the sense amplifier detects the data value.

摘要翻译： 提供了可用于减少存储器电路消耗的功率的技术。 在一个示例中，可编程逻辑器件（PLD）包括适于为预期用途配置PLD的多个静态随机存取存储器（SRAM）单元。 一对位线连接到SRAM单元。 SRAM单元中的至少一个适于在读操作期间响应于由SRAM单元之一接收的字线信号而向位线提供数据信号。 感测放大器连接到位线，并适于响应于在读取操作期间由读出放大器接收的触发信号，从数据信号中检测数据值。 逻辑适于相对于字线信号延迟触发信号，以允许数据信号在感测放大器检测到数据值之前稳定。

公开(公告)号：US08351287B1

公开(公告)日：2013-01-08

申请号：US12976412

申请日：2010-12-22

申请人： Rohith Sood ,  Fabiano Fontana ,  Zheng Chen

发明人： Rohith Sood ,  Fabiano Fontana ,  Zheng Chen

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  H03K19/0008 ,  H03K19/0016

摘要： Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.

摘要翻译： 提供了可用于减少存储器电路消耗的功率的技术。 在一个示例中，存储器电路包括静态随机存取存储器（SRAM）单元。 一对位线连接到SRAM单元。 预充电电路连接到位线。 预充电电路适用于在对SRAM单元进行读和写操作之前立即对位线进行预充电，而在其它时间相对于位线浮动。