公开(公告)号：US07800250B2

公开(公告)日：2010-09-21

申请号：US12107531

申请日：2008-04-22

申请人： Richard Hull ,  Vivien Delport ,  Zacharias Marthinus Smit ,  Sean Steedman ,  Jerrold S. Zdenek ,  Michael Charles ,  Ruan Lourens

发明人： Richard Hull ,  Vivien Delport ,  Zacharias Marthinus Smit ,  Sean Steedman ,  Jerrold S. Zdenek ,  Michael Charles ,  Ruan Lourens

IPC分类号： H01H47/02

CPC分类号： G11C5/147 ,  Y10T307/74 ,  Y10T307/747 ,  Y10T307/858

摘要： An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

摘要翻译： 集成电路器件提供可选择用于将外部滤波器/稳定电容器耦合到内部稳压器的外部引脚（连接）的选择。 然而，通过低阻抗路径将内部稳压器的输出连接到不带电的外部滤波器/稳定电容器（或者与内部调节电压相比，被充电到不同电压电平的电容器）可能会导致稳压器输出电压下垂/尖峰 如果内部电压调节器试图将电容器上/下放电到稳压器输出电压的平衡。 为了最小化该潜在的下垂/尖峰，可以以受控的方式将外部滤波器/稳定电容器上的电压调节到与内部电压调节器的输出端上的电压基本相同的电压，然后内部电压调节器可操作地耦合 通过低阻抗到外部调节滤波器/稳定电容器。

公开(公告)号：US20080272830A1

公开(公告)日：2008-11-06

申请号：US11744365

申请日：2007-05-04

申请人： Sean Steedman ,  Ruan Lourens ,  Richard Hull

发明人： Sean Steedman ,  Ruan Lourens ,  Richard Hull

IPC分类号： G11C5/14

CPC分类号： H03K17/22 ,  G01R19/16552 ,  G06F1/24 ,  G06F1/30 ,  H03K2217/0036

摘要： A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

摘要翻译： 具有可编程功率和响应时间特性的欠压复位电路。 这些特性可以通过n位宽的总线进行编程，以实现从非常低的功耗和较慢的响应时间到非常快的响应时间和更高的功耗的两个不同的特性。 可以使用串行一线总线来代替n位宽的总线。

公开(公告)号：US07324615B2

公开(公告)日：2008-01-29

申请号：US10736372

申请日：2003-12-15

申请人： Ruan Lourens ,  Layton W. Eagar ,  Russell Eugene Cooper

发明人： Ruan Lourens ,  Layton W. Eagar ,  Russell Eugene Cooper

IPC分类号： H04B1/00 ,  H04B1/18

CPC分类号： H04B1/24 ,  G04R20/10 ,  H03H11/1252 ,  H03H11/1291

摘要： A time signal receiver and decoder receives, detects and stores time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. The time signal receiver may use a high-Q state variable bandpass filter or an anti-notch filter circuit for selectivity at the time signal frequency of interest. The decoder is coupled to the time signal receiver, decodes the time information in the received time signal and may store the decoded time information.

摘要翻译： 时间信号接收器和解码器接收，检测和存储来自时间信号的时间信息，例如WWV，WWVH，WWVB（USA），JJY（Japan），MSF（UK）等。 时间信息可以用于自设置时钟，并且时钟可以用作时间敏感应用，设备和系统中的参考。 时间信号接收机可以在感兴趣的时间信号频率下使用高Q状态可变带通滤波器或抗陷波滤波器电路用于选择性。 解码器耦合到时间信号接收器，对接收的时间信号中的时间信息进行解码并且可以存储解码的时间信息。

公开(公告)号：US20050237163A1

公开(公告)日：2005-10-27

申请号：US11079719

申请日：2005-03-14

申请人： Thomas Lee ,  James Nolan ,  Steve Vernier ,  Ruan Lourens ,  Vivien Delport ,  Alan Lamphier ,  Glen Sullivan

发明人： Thomas Lee ,  James Nolan ,  Steve Vernier ,  Ruan Lourens ,  Vivien Delport ,  Alan Lamphier ,  Glen Sullivan

IPC分类号： G06K19/07 ,  G07C9/00 ,  H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0726 ,  G06K19/07767

摘要： A multi-channel remote keyless entry (RKE) transponder having dynamically re-configurable input channel selection, channel disable, settable sensitivity for each channel, wake-up filter timing parameters, automatic gain control hold, internal tuning capacitor selection for each channel's antenna, minimum modulation depth requirement for input signal and bi-directional talk-back. Programmable minimum modulation depth requirement reduces false wake-up of the RKE transponder. An antenna for each channel of the RKE transponder may be tuned with internal tuning capacitors for improved range and receiver sensitivity. The internal tuning capacitor parameters may be stored in a configuration register. Gain of the channel may be fixed while the antenna is tuned. The antennas may be de-queued for talk-back to a base station for low frequency bi-directional communications. An external control device may dynamically read from and write to the configuration registers via a serial communications interface.

摘要翻译： 具有动态可重配置的输入通道选择，通道禁用，每个通道的可设置灵敏度，唤醒滤波器定时参数，自动增益控制保持，每个通道天线的内部调谐电容选择的多通道遥控无钥匙进入（RKE） 输入信号和双向对讲的最小调制深度要求。 可编程的最小调制深度要求可减少RKE转发器的假唤醒。 可以使用内部调谐电容器调整RKE应答器的每个通道的天线，以提高范围和接收机灵敏度。 内部调谐电容参数可以存储在配置寄存器中。 天线调谐时，通道的增益可能会固定。 天线可以被排队，用于与基站通话用于低频双向通信。 外部控制设备可以通过串行通信接口动态地读取和写入配置寄存器。

公开(公告)号：US20050237160A1

公开(公告)日：2005-10-27

申请号：US11079765

申请日：2005-03-14

申请人： James Nolan ,  Thomas Lee ,  Alan Lamphier ,  Ruan Lourens ,  Steve Vernier

发明人： James Nolan ,  Thomas Lee ,  Alan Lamphier ,  Ruan Lourens ,  Steve Vernier

IPC分类号： G06K7/00 ,  G06K19/07 ,  G07C9/00 ,  H04Q5/22

CPC分类号： G06K19/0705 ,  G06K19/0723 ,  G07C9/00309 ,  G07C2009/0038

摘要： A bidirectional remote keyless entry (RKE) transponder comprises an analog front-end (AFE) having a programmable wake-up filter that predefines the waveform timing of the desired input signal, minimum modulation depth requirement of input signal, and independently controllable channel gain reduction of each of its three channels, X, Y, and Z. The wake-up filter parameters are the length of high and low durations of wake-up pulses that may be programmed in a configuration register. The wake-up filter allows the AFE to output demodulated data if the input signal meets its wake-up filter requirement, but does not output the demodulated data otherwise. The AFE output pin is typically connected to an external device for control, such as a microcontroller (MCU). The external device typically stays in low current sleep (or standby) mode when the AFE has no output and switches to high current wake-up (or active) mode when the AFE has output. Therefore, in order to keep the external control device in the low current sleep mode when there is no desired input signal, it is necessary to keep no output at the AFE output pin. This can be achieved by controlling the wake-up filter parameters, minimum modulation depth requirement of input signal, and channel gains of the AFE device. These features can reduce false-wake up of the bidirectional RKE transponder due to undesired input signals such as noise signals.

摘要翻译： 双向远程无钥匙进入（RKE）转发器包括具有可编程唤醒滤波器的模拟前端（AFE），其预定义所需输入信号的波形定时，输入信号的最小调制深度要求以及独立可控的信道增益减小 的三个通道中的每一个，X，Y和Z.唤醒滤波器参数是可以在配置寄存器中编程的唤醒脉冲的高和低持续时间的长度。 唤醒滤波器允许AFE在输入信号满足唤醒滤波器要求时输出解调数据，否则不输出解调数据。 AFE输出引脚通常连接到外部设备进行控制，例如微控制器（MCU）。 当AFE没有输出时，外部设备通常保持在低电流休眠（或待机）模式，并且当AFE输出时，外部设备切换到高电流唤醒（或有效）模式。 因此，为了在不需要输入信号的情况下将外部控制装置保持在低电流休眠模式，必须在AFE输出引脚处不输出。 这可以通过控制唤醒滤波器参数，输入信号的最小调制深度要求和AFE设备的通道增益来实现。 这些功能可以减少由于不期望的输入信号（如噪声信号）引起的双向RKE转发器的假唤醒。

公开(公告)号：US20080272657A1

公开(公告)日：2008-11-06

申请号：US12107531

申请日：2008-04-22

申请人： Richard HULL ,  Vivien DELPORT ,  Zacharias Marthinus SMIT ,  Sean STEEDMAN ,  Jerrold S. ZDENEK ,  Michael CHARLES ,  Ruan LOURENS

发明人： Richard HULL ,  Vivien DELPORT ,  Zacharias Marthinus SMIT ,  Sean STEEDMAN ,  Jerrold S. ZDENEK ,  Michael CHARLES ,  Ruan LOURENS

IPC分类号： H01H47/00 ,  H02B1/24

CPC分类号： G11C5/147 ,  Y10T307/74 ,  Y10T307/747 ,  Y10T307/858

摘要： An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

摘要翻译： 集成电路器件提供可选择用于将外部滤波器/稳定电容器耦合到内部稳压器的外部引脚（连接）的选择。 然而，通过低阻抗路径将内部稳压器的输出连接到不带电的外部滤波器/稳定电容器（或者与内部调节电压相比，被充电到不同电压电平的电容器）可能会导致稳压器输出电压下垂/尖峰 如果内部电压调节器试图将电容器上/下放电到稳压器输出电压的平衡。 为了最小化该潜在的下垂/尖峰，可以以受控的方式将外部滤波器/稳定电容器上的电压调节到与内部电压调节器的输出端上的电压基本相同的电压，然后内部电压调节器可操作地耦合 通过低阻抗到外部调节滤波器/稳定电容器。

公开(公告)号：US06922084B2

公开(公告)日：2005-07-26

申请号：US10764919

申请日：2004-01-26

申请人： Ruan Lourens ,  Miguel Moreno

发明人： Ruan Lourens ,  Miguel Moreno

IPC分类号： G01K3/00 ,  G01R19/00 ,  G01R19/165 ,  G01R31/36 ,  G01R31/40 ,  H01L35/00 ,  H02J7/00 ,  H02P9/30 ,  H03K5/06 ,  H03K5/08 ,  H03K5/153

CPC分类号： G01K3/005 ,  G01K2215/00 ,  G01R19/16542 ,  G01R31/3648 ,  H03K5/06 ,  H03K5/08

摘要： An Ultra-low power voltage detection circuit is implemented in a digital integrated circuit to device to provide a basic timer, programmable timer and programmable low voltage detection (PLVD) using a single connection of the digital integrated circuit device and a passive component(s) external to the digital integrated circuit device. An internal low current source may be enabled so as to discharge an external timing capacitor connected to the output connection, thus eliminating the need for an external resistor. However, timing accuracy may be improved by adding an external discharging resistor and/or charging resistor. The output connection may be configured as a tri-state output and may be driven high to charge and low to discharge the timing capacitor. A voltage reference may be used in determining a voltage trip point for timing and low voltage detection purposes. Temperature may be determined from either a trip voltage compared to a known voltage determined at a known temperature, or a current value of the current source compared to a known current value determined at a known temperature, times a constant.

摘要翻译： 在设备的数字集成电路中实现超低功率电压检测电路，以使用数字集成电路器件的单个连接和无源部件提供基本定时器，可编程定时器和可编程低电压检测（PLVD） 在数字集成电路设备外部。 可以使能内部低电流源，以便连接到输出连接的外部定时电容器放电，从而不需要外部电阻器。 然而，通过添加外部放电电阻器和/或充电电阻器可以提高定时精度。 输出连接可以被配置为三态输出，并且可以被驱动为高电荷并且使得定时电容器放电低。 电压参考可用于确定用于定时和低电压检测目的的电压跳变点。 温度可以由与在已知温度下确定的已知电压相比的跳闸电压或电流源的电流值与在已知温度下确定的已知电流值乘以常数来确定。

公开(公告)号：US20050141648A1

公开(公告)日：2005-06-30

申请号：US10746590

申请日：2003-12-24

申请人： Ruan Lourens ,  Douglas Chaffee

发明人： Ruan Lourens ,  Douglas Chaffee

IPC分类号： H04B1/24 ,  H04L27/06 ,  H03D1/00

CPC分类号： H04B1/24

摘要： A time signal peripheral may include a radio receiver, decoder/demodulator and time registers. The time signal peripheral may receive, detect and store time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. A digital processor may be coupled to and control the time signal peripheral. The digital processor may be used to decode the time information in the received time signal, store the decoded time information and make the time information available for use by a device and/or system, or the time signal peripheral may do these functions, allowing the digital processor to be used for higher level applications. The time signal peripheral may be fabricated on an integrated circuit die with or without the digital processor. The time signal peripheral and the digital process may be on a separate integrated circuit dice and be packaged together in a signal integrated circuit package.

摘要翻译： 时间信号外围设备可以包括无线电接收机，解码器/解调器和时间寄存器。 时间信号外围设备可以接收，检测和存储来自时间信号的时间信息，例如WWV，WWVH，WWVB（USA），JJY（Japan），MSF（UK）等。 时间信息可以用于自设置时钟，并且时钟可以用作时间敏感应用，设备和系统中的参考。 数字处理器可以耦合到并控制时间信号外围设备。 数字处理器可以用于解码所接收的时间信号中的时间信息，存储解码的时间信息并使得时间信息可供设备和/或系统使用，或者时间信号外设可以执行这些功能，从而允许 数字处理器用于更高级别的应用。 时间信号外围设备可以在具有或不具有数字处理器的集成电路管芯上制造。 时间信号外围设备和数字处理器可以在单独的集成电路芯片上并且封装在信号集成电路封装中。

公开(公告)号：US20050129156A1

公开(公告)日：2005-06-16

申请号：US10736372

申请日：2003-12-15

申请人： Ruan Lourens ,  Layton Eagar ,  Russell Cooper

发明人： Ruan Lourens ,  Layton Eagar ,  Russell Cooper

IPC分类号： G04G5/00 ,  G04G7/02 ,  H03H11/12 ,  H04B1/24 ,  H04B1/10

CPC分类号： H04B1/24 ,  G04R20/10 ,  H03H11/1252 ,  H03H11/1291

摘要： A time signal receiver and decoder receives, detects and stores time information from time signals, e.g., WWV, WWVH, WWVB (USA), JJY (Japan), MSF (UK) and the like. The time information may be used for a self setting clock, and the clock may be used as a reference in time sensitive applications, devices and systems. The time signal receiver may use a high-Q state variable bandpass filter or an anti-notch filter circuit for selectivity at the time signal frequency of interest. The decoder is coupled to the time signal receiver, decodes the time information in the received time signal and may store the decoded time information.

摘要翻译： 时间信号接收器和解码器接收，检测和存储来自时间信号的时间信息，例如WWV，WWVH，WWVB（USA），JJY（Japan），MSF（UK）等。 时间信息可以用于自设置时钟，并且时钟可以用作时间敏感应用，设备和系统中的参考。 时间信号接收机可以在感兴趣的时间信号频率下使用高Q状态可变带通滤波器或抗陷波滤波器电路用于选择性。 解码器耦合到时间信号接收器，对接收的时间信号中的时间信息进行解码并且可以存储解码的时间信息。

公开(公告)号：US08080983B2

公开(公告)日：2011-12-20

申请号：US12604597

申请日：2009-10-23

申请人： Ruan Lourens ,  Razvan Enachescu ,  Marc Tiu

发明人： Ruan Lourens ,  Razvan Enachescu ,  Marc Tiu

IPC分类号： G05F1/565 ,  G05F5/00

CPC分类号： G05F1/575

摘要： A power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.

摘要翻译： 在低压降（LDO）旁路电压调节器中使用电源元件旁路和电压调节电路关闭，以最小化当电源输入电压接近稳压电路的稳压输出电压时由电压调节器电路汲取的电流。 低压降（LDO）旁路电压调节器采用两种工作模式。 当电源输入电压大于参考电压输入时，使用调节模式，当电源输入电压小于或等于电压调节电路的稳压输出电压时，使用轨迹模式。 在调节和跟踪操作模式之间切换时可能会引入迟滞。