Subranging analog to digital converter with multi-phase clock timing
    1.
    发明授权
    Subranging analog to digital converter with multi-phase clock timing 有权
    使用多相时钟定时将模数转换器分段

    公开(公告)号:US07324038B2

    公开(公告)日:2008-01-29

    申请号:US10625702

    申请日:2003-07-24

    CPC classification number: H03M1/146 H03K17/04106 H03M1/204 H03M1/365

    Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

    Abstract translation: N位模数转换器包括参考梯形图,连接到输入电压的跟踪和保持放大器,在其输入处连接到粗略电容器的粗略ADC放大器,并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位,精细ADC放大器在其输入端连接到精细电容器,并具有由两相时钟的第二时钟相位控制的精细ADC复位开关,开关矩阵从第二时钟相位选择电压子范围 参考梯形图,用于基于粗ADC放大器的输出的精细ADC放大器使用,并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压,并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围,并且在第二时钟相位期间连接到T / H输出;以及编码器,其将粗略和精细ADC放大器的输出转换为Nb 它输出。

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