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公开(公告)号：US06831585B2
公开(公告)日：2004-12-14
申请号：US10684444
申请日：2003-10-15
IPC分类号： H03M112
CPC分类号： H03K17/04106 , H03M1/0646 , H03M1/146 , H03M1/204 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
摘要翻译： 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。
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公开(公告)号：US06628224B1
公开(公告)日：2003-09-30
申请号：US10153709
申请日：2002-05-24
IPC分类号： H03M112
CPC分类号： H03K17/04106 , H03M1/0646 , H03M1/146 , H03M1/204 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
摘要翻译： 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。
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公开(公告)号：US20130342378A1
公开(公告)日：2013-12-26
申请号：US13529282
申请日：2012-06-21
IPC分类号： H03M1/66
CPC分类号： H03M1/0617 , H03M1/0682 , H03M1/742
摘要： In one method embodiment, receiving a data signal; and converting the data signal to an analog signal over plural clock cycles, the converting comprising: during a first clock cycle of the plural clock cycles, switching on one or more first current cells of a first bank while simultaneously a second bank comprising second current cells is switched off or almost off; and during a second clock cycle of the plural clock cycles, the second clock cycle immediately subsequent to the first clock cycle, switching on one or more of the second current cells of the second bank while simultaneously the first bank is switched off or almost off.
摘要翻译： 在一个方法实施例中，接收数据信号; 以及在多个时钟周期内将所述数据信号转换为模拟信号，所述转换包括：在所述多个时钟周期的第一时钟周期期间，接通第一存储体的一个或多个第一当前单元，同时包含第二存储单元 被关闭或几乎关闭; 并且在所述多个时钟周期的第二时钟周期期间，紧接着所述第一时钟周期之后的所述第二时钟周期，接通所述第二存储体的一个或多个第二电流单元，同时所述第一存储体被切断或几乎关闭。
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公开(公告)号：US07859338B2
公开(公告)日：2010-12-28
申请号：US12177523
申请日：2008-07-22
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/0205 , H03F1/083 , H03F3/3023 , H03F3/45183 , H03F2200/153 , H03F2203/30015 , H03F2203/30033 , H03F2203/30084 , H03F2203/30117 , H03F2203/45292 , H03F2203/45626
摘要： A compact low-power class AB power amplifier design is provided. In an embodiment, the amplifier design eliminates an intermediate stage that couples an input stage and a biasing mesh of the amplifier. In another embodiment, the amplifier design reuses a tail current from the input stage to bias the biasing mesh. Accordingly, a much higher power efficiency can be achieved using the proposed amplifier design compared to conventional class AB amplifiers. Further, the proposed amplifier design is extremely compact and occupies a small silicon area.
摘要翻译： 提供紧凑型低功耗AB类功率放大器设计。 在一个实施例中，放大器设计消除了耦合输入级和放大器的偏置网格的中间级。 在另一个实施例中，放大器设计重新使用来自输入级的尾部电流来偏置偏置网。 因此，与传统的AB类放大器相比，使用所提出的放大器设计可以实现更高的功率效率。 此外，所提出的放大器设计非常紧凑，占用小的硅面积。
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公开(公告)号：US20090027122A1
公开(公告)日：2009-01-29
申请号：US12177523
申请日：2008-07-22
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/0205 , H03F1/083 , H03F3/3023 , H03F3/45183 , H03F2200/153 , H03F2203/30015 , H03F2203/30033 , H03F2203/30084 , H03F2203/30117 , H03F2203/45292 , H03F2203/45626
摘要： A compact low-power class AB power amplifier design is provided. In an embodiment, the amplifier design eliminates an intermediate stage that couples an input stage and a biasing mesh of the amplifier. In another embodiment, the amplifier design reuses a tail current from the input stage to bias the biasing mesh. Accordingly, a much higher power efficiency can be achieved using the proposed amplifier design compared to conventional class AB amplifiers. Further, the proposed amplifier design is extremely compact and occupies a small silicon area.
摘要翻译： 提供紧凑型低功耗AB类功率放大器设计。 在一个实施例中，放大器设计消除了耦合输入级和放大器的偏置网格的中间级。 在另一个实施例中，放大器设计重新使用来自输入级的尾部电流来偏置偏置网。 因此，与传统的AB类放大器相比，使用所提出的放大器设计可以实现更高的功率效率。 此外，所提出的放大器设计非常紧凑，占用小的硅面积。
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公开(公告)号：US07324038B2
公开(公告)日：2008-01-29
申请号：US10625702
申请日：2003-07-24
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。
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公开(公告)号：US06664910B1
公开(公告)日：2003-12-16
申请号：US10460622
申请日：2003-06-13
IPC分类号： H03M112
CPC分类号： H03K17/04106 , H03M1/0646 , H03M1/146 , H03M1/204 , H03M1/206 , H03M1/361 , H03M1/365
摘要： An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.
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公开(公告)号：US06653966B1
公开(公告)日：2003-11-25
申请号：US10359201
申请日：2003-02-06
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M100
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。
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公开(公告)号：US20090155222A1
公开(公告)日：2009-06-18
申请号：US12184907
申请日：2008-08-01
CPC分类号： C12N5/0606 , C12N15/1138 , C12N2310/111 , C12N2310/14 , C12N2501/58
摘要： There is provided a method of retarding differentiation of a biological cell, the method comprising culturing the cell in the presence of an inhibitor of E-cadherin activity. The method is particularly advantageous in retarding the differentiation of stem or progenitor cells, and allows suspension culture of such cells in a manner that enables large scale expansion of cell populations. There is also provided a stem or progenitor cell comprising a construct encoding an inhibitor of E-cadherin activity; and a cell culture medium, for use in the retardation of biological cell differentiation, comprising an inhibitor of E-cadherin activity.
摘要翻译： 提供了延缓生物细胞分化的方法，该方法包括在E-钙粘蛋白活性抑制剂存在下培养细胞。 该方法特别有利于延缓干细胞或祖细胞的分化，并允许以能够大规模扩增细胞群体的方式悬浮培养这些细胞。 还提供了包含编码E-钙粘蛋白活性抑制剂的构建体的干细胞或祖细胞; 以及用于延迟生物细胞分化的细胞培养基，其包含E-钙粘蛋白活性的抑制剂。
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公开(公告)号：US06583747B1
公开(公告)日：2003-06-24
申请号：US10158773
申请日：2002-05-31
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M112
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
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