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公开(公告)号：US20100158514A1
公开(公告)日：2010-06-24
申请号：US12639086
申请日：2009-12-16
申请人： Ryoji AZUMI , Takashi Umegaki , Shigeo Tani , Shosaku Yamasaki
发明人： Ryoji AZUMI , Takashi Umegaki , Shigeo Tani , Shosaku Yamasaki
CPC分类号： H04J3/14 , H04J2203/006
摘要： A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.
摘要翻译： 网络装置包括：输入接口单元; 第一和第二线路交换单元将来自输入接口单元的输出信号交叉连接; 输出接口单元，包括：选择单元，用于选择来自第一或第二行切换单元的输出; 和一个CPU。 线路切换单元各自包括：控制信号生成单元，其将设置数据存储在存储器中，并且基于设置数据生成线路切换控制信号; 存储器错误检测处理单元，检测存储器错误并输出错误信息; 以及主信号处理单元，当未检测到错误时将设置数据写入缓冲器，并且当检测到错误时保持存储在缓冲器中的设置数据，并且根据存储在缓冲器中的设置数据执行交叉连接处理。 CPU根据错误信息控制选择单元。
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公开(公告)号：US09166739B2
公开(公告)日：2015-10-20
申请号：US13488741
申请日：2012-06-05
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/6561
摘要： An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.
摘要翻译： 纠错处理电路包括：分割电路，将输入数据分割为预定数据长度的多个片段; 多个并行设置的运算电路，分别对由分割电路分割的多条数据进行纠错运算; 多路复用电路，对由多个运算电路进行了运算的多条数据进行复用; 以及输出由多路复用电路复用的数据的输出电路。
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公开(公告)号：US08355318B2
公开(公告)日：2013-01-15
申请号：US12608528
申请日：2009-10-29
申请人： Mitsuhiro Kawaguchi , Shigeo Tani , Ryoji Azumi , Hideki Matsui
发明人： Mitsuhiro Kawaguchi , Shigeo Tani , Ryoji Azumi , Hideki Matsui
IPC分类号： G01R31/08
CPC分类号： H04L12/437
摘要： There is provided a node apparatus having a plurality of interface units for interfacing to a transmission line, switch units of a work system and a protection system for switching signals of the transmission line, and a service selector used to relieve a network failure over ring networks interconnected by node apparatuses, the node apparatus including a first controller for controlling the service selector in the switch units, and a second controller for controlling setting information of alarm detection in case of using the service selector in the interface units.
摘要翻译： 提供了一种节点装置，其具有用于与传输线接口的多个接口单元，工作系统的开关单元和用于切换传输线的信号的保护系统，以及用于通过环形网络来减轻网络故障的服务选择器 所述节点装置包括用于控制所述开关单元中的所述服务选择器的第一控制器，以及用于在所述接口单元中使用所述服务选择器的情况下控制警报检测的设置信息的第二控制器。
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4.发明授权Network apparatus that determines whether data is written into buffer based on detection of a memory error 有权基于检测到存储器错误确定数据是否被写入缓冲器的网络设备公开(公告)号：US08295161B2
公开(公告)日：2012-10-23
申请号：US12639086
申请日：2009-12-16
申请人： Ryoji Azumi , Takashi Umegaki , Shigeo Tani , Shosaku Yamasaki
发明人： Ryoji Azumi , Takashi Umegaki , Shigeo Tani , Shosaku Yamasaki
IPC分类号： H04L1/22
CPC分类号： H04J3/14 , H04J2203/006
摘要： A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.
摘要翻译： 网络装置包括：输入接口单元; 第一和第二线路交换单元将来自输入接口单元的输出信号交叉连接; 输出接口单元，包括：选择单元，用于选择来自第一或第二行切换单元的输出; 和一个CPU。 线路切换单元各自包括：控制信号生成单元，其将设置数据存储在存储器中，并且基于设置数据生成线路切换控制信号; 存储器错误检测处理单元，检测存储器错误并输出错误信息; 以及主信号处理单元，当未检测到错误时将设置数据写入缓冲器，并且当检测到错误时保持存储在缓冲器中的设置数据，并且根据存储在缓冲器中的设置数据执行交叉连接处理。 CPU根据错误信息控制选择单元。
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5.发明申请公开(公告)号：US20120331364A1
公开(公告)日：2012-12-27
申请号：US13488741
申请日：2012-06-05
IPC分类号： G06F11/07
CPC分类号： H04L1/0052 , H03M13/1515 , H03M13/6561
摘要： An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.
摘要翻译： 纠错处理电路包括：分割电路，将输入数据分割为预定数据长度的多个片段; 多个并行设置的运算电路，分别对由分割电路分割的多条数据进行纠错运算; 多路复用电路，对由多个运算电路进行了运算的多条数据进行复用; 以及输出由多路复用电路复用的数据的输出电路。
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公开(公告)号：US20110170864A1
公开(公告)日：2011-07-14
申请号：US12987672
申请日：2011-01-10
IPC分类号： H04J14/00
CPC分类号： H04J3/1652
摘要： An interface device for demultiplexing, from a first frame in a transport network, a plurality of second frames multiplexed into the first frame is provided. The interface device includes an extractor configured to extract a plurality of data groups to constitute the first frame, and a second frame generator configured to create the second frames based on the plurality of data groups extracted by the extractor.
摘要翻译： 提供了一种用于从传输网络中的第一帧解复用多路复用到第一帧中的多个第二帧的接口设备。 接口装置包括提取器，被配置为提取多个数据组以构成第一帧;以及第二帧生成器，被配置为基于由提取器提取的多个数据组来创建第二帧。
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公开(公告)号：US20100124417A1
公开(公告)日：2010-05-20
申请号：US12608528
申请日：2009-10-29
申请人： Mitsuhiro KAWAGUCHI , Shigeo TANI , Ryoji AZUMI , Hideki MATSUI
发明人： Mitsuhiro KAWAGUCHI , Shigeo TANI , Ryoji AZUMI , Hideki MATSUI
IPC分类号： H04B10/00
CPC分类号： H04L12/437
摘要： There is provided a node apparatus having a plurality of interface units for interfacing to a transmission line, switch units of a work system and a protection system for switching signals of the transmission line, and a service selector used to relieve a network failure over ring networks interconnected by node apparatuses, the node apparatus including a first controller for controlling the service selector in the switch units, and a second controller for controlling setting information of alarm detection in case of using the service selector in the interface units.
摘要翻译： 提供了一种节点装置，其具有用于与传输线接口的多个接口单元，工作系统的开关单元和用于切换传输线的信号的保护系统，以及用于通过环形网络来减轻网络故障的服务选择器 所述节点装置包括用于控制所述开关单元中的所述服务选择器的第一控制器，以及用于在所述接口单元中使用所述服务选择器的情况下控制警报检测的设置信息的第二控制器。
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