公开(公告)号：US20170053923A1

公开(公告)日：2017-02-23

申请号：US15239121

申请日：2016-08-17

Applicant: CHUL-JIN HWANG ,  PAN-SUK KWAK ,  SEOK-JUN HAM

Inventor： CHUL-JIN HWANG ,  PAN-SUK KWAK ,  SEOK-JUN HAM

IPC: H01L27/115 ,  G11C16/06 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C5/025 ,  G11C16/0483 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  H01L28/00

Abstract: A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.

Abstract translation: 如下提供非易失性存储器件。 衬底具有外围电路。 第一半导体层设置在基板上。 第一半导体层包括存储单元区域。 第一栅极结构设置在第一半导体层上。 第一栅极结构包括沿垂直于第一半导体层的方向堆叠的多个第一栅电极和穿过多个第一栅电极的多个垂直沟道结构。 第一栅极结构布置在存储单元区域中。 第二栅极结构设置在基板上。 第二栅极结构包括沿垂直于第一半导体层的方向堆叠的多个第二栅电极。 第二栅极结构布置在存储单元区域的外部。