公开(公告)号：US10521152B2

公开(公告)日：2019-12-31

申请号：US15711129

申请日：2017-09-21

申请人： Dongjin Park ,  Kilhwan Kim ,  Seonghoon Woo

发明人： Dongjin Park ,  Kilhwan Kim ,  Seonghoon Woo

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/10

摘要： A storage device includes a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are configured to distributively store first and second stripes of a stripe set. The controller includes a first memory and a second memory within the controller. The controller is configured to receive the first and second stripes from a host, distributively store the first and second stripes in the plurality of nonvolatile memories, and to perform a parity operation based on the first and second stripes. The controller is configured to generate intermediate parity based on the first stripe and store the intermediate parity in the first memory. If the parity operation is stopped, the controller is configured to move the intermediate parity stored in the first memory to the second memory.

公开(公告)号：US09767053B2

公开(公告)日：2017-09-19

申请号：US14102979

申请日：2013-12-11

申请人： Seonghoon Woo ,  Haksun Kim ,  Euihyeok Kwon ,  Jaegeun Park

发明人： Seonghoon Woo ,  Haksun Kim ,  Euihyeok Kwon ,  Jaegeun Park

IPC分类号： G06F13/16

CPC分类号： G06F13/1673 ,  Y02D10/14

摘要： A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.

公开(公告)号：US20180129451A1

公开(公告)日：2018-05-10

申请号：US15711129

申请日：2017-09-21

申请人： Dongjin Park ,  Kilhwan Kim ,  Seonghoon Woo

发明人： Dongjin Park ,  Kilhwan Kim ,  Seonghoon Woo

IPC分类号： G06F3/06 ,  G06F11/10

摘要： A storage device includes a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are configured to distributively store first and second stripes of a stripe set. The controller includes a first memory and a second memory within the controller. The controller is configured to receive the first and second stripes from a host, distributively store the first and second stripes in the plurality of nonvolatile memories, and to perform a parity operation based on the first and second stripes. The controller is configured to generate intermediate parity based on the first stripe and store the intermediate parity in the first memory. If the parity operation is stopped, the controller is configured to move the intermediate parity stored in the first memory to the second memory.

公开(公告)号：US20130179659A1

公开(公告)日：2013-07-11

申请号：US13617786

申请日：2012-09-14

申请人： MANKEUN SEO ,  DAEWOOK KIM ,  HONG RAK SON ,  JUNJIN KONG ,  SEONGHOON WOO ,  SOONJAE WON ,  PILSANG YOON

发明人： MANKEUN SEO ,  DAEWOOK KIM ,  HONG RAK SON ,  JUNJIN KONG ,  SEONGHOON WOO ,  SOONJAE WON ,  PILSANG YOON

IPC分类号： G06F12/00

CPC分类号： G06F12/023 ,  G06F3/0656 ,  G06F3/0661 ,  G06F2212/401 ,  Y02D10/13

摘要： A memory controller comprises a host interface block comprising a compression ratio calculator configured to determine whether a compression ratio of input data exceeds a predetermined compression ratio, and a compression block configured to compress the input data as a consequence of the host compression ratio calculator determining that the compression ratio exceeds the predetermined compression ratio.

摘要翻译： 存储器控制器包括：主机接口块，包括：压缩比计算器，被配置为确定输入数据的压缩比是否超过预定压缩比;以及压缩块，其被配置为压缩输入数据，作为主压缩比计算器确定 压缩比超过预定压缩比。

公开(公告)号：US08954693B2

公开(公告)日：2015-02-10

申请号：US13617786

申请日：2012-09-14

申请人： Mankeun Seo ,  Daewook Kim ,  Hong Rak Son ,  Junjin Kong ,  Seonghoon Woo ,  Soonjae Won ,  Pilsang Yoon

发明人： Mankeun Seo ,  Daewook Kim ,  Hong Rak Son ,  Junjin Kong ,  Seonghoon Woo ,  Soonjae Won ,  Pilsang Yoon

IPC分类号： G06F12/04

CPC分类号： G06F12/023 ,  G06F3/0656 ,  G06F3/0661 ,  G06F2212/401 ,  Y02D10/13

摘要： A memory controller comprises a host interface block comprising a compression ratio calculator configured to determine whether a compression ratio of input data exceeds a predetermined compression ratio, and a compression block configured to compress the input data as a consequence of the host compression ratio calculator determining that the compression ratio exceeds the predetermined compression ratio.

摘要翻译： 存储器控制器包括：主机接口块，包括：压缩比计算器，被配置为确定输入数据的压缩比是否超过预定压缩比;以及压缩块，其被配置为压缩输入数据，作为主压缩比计算器确定 压缩比超过预定压缩比。

公开(公告)号：US20130124784A1

公开(公告)日：2013-05-16

申请号：US13604735

申请日：2012-09-06

申请人： SEONGHOON WOO ,  HAKSUN KIM

发明人： SEONGHOON WOO ,  HAKSUN KIM

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

摘要： A method of programming a nonvolatile memory device comprises receiving write data, detecting an address of a multi-level cell area associated with the write data, randomizing the write data using the address and programming the randomized data in a single-level cell area.

摘要翻译： 非易失性存储器件的编程方法包括接收写入数据，检测与写入数据相关联的多级单元区域的地址，使用该地址对写入数据进行随机化，并对单级单元区域中的随机数据进行编程。

公开(公告)号：US20140164673A1

公开(公告)日：2014-06-12

申请号：US14102979

申请日：2013-12-11

申请人： Seonghoon WOO ,  Haksun KIM ,  Euihyeok KWON ,  Jaegeun PARK

发明人： Seonghoon WOO ,  Haksun KIM ,  Euihyeok KWON ,  Jaegeun PARK

IPC分类号： G06F13/16 ,  G06F13/40 ,  G11C7/10

CPC分类号： G06F13/1673 ,  Y02D10/14

摘要： A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.

摘要翻译： 提供了通过多个通道与存储介质连接的存储器控​​制器，其包括包括多个信号处理引擎的信号处理块; 以及解码调度器，其被配置为控制数据路径，使得所述多个信号处理引擎中的至少一个激活信号处理引擎分别与所述多个信道连接。