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公开(公告)号：US20240218564A1
公开(公告)日：2024-07-04
申请号：US18537785
申请日：2023-12-12
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Wenkai LIU , Zhongying XUE , Yun LIU , Rongwang DAI , Minghao LI , Yuehui YU
CPC分类号： C30B30/04 , C30B15/20 , C30B29/06 , H01F6/06 , H01L27/1203
摘要： The present invention provides a crystal growing method, an apparatus and a RF-SOI substrate for growing a crystal. The crystal growing method may comprise: controlling a first superconducting coil to generate a first current, and controlling a second superconducting coil to generate a second current, wherein a value of the first current is not equal to a value of the second current, the first superconducting coil and the second superconducting coil are superconducting coils positioned oppositely outside a crucible to generate a magnetic field in the crucible; and pulling upwards to grow a monocrystalline in an asymmetric magnetic field generated by the first current and the second current in the crucible.
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2.发明公开公开(公告)号：US20240141547A1
公开(公告)日：2024-05-02
申请号：US18177724
申请日：2023-03-02
发明人： Xing Wei , Ming Hao Li , Rong Wang Dai , Zi Wen Wang , Zhong Ying Xue
摘要： The present invention relates to a preparation method of a P-type high-resistance and ultra-high-resistance Czochralski monocrystalline silicon substrate. According to the present invention, an oxygen concentration in a silicon wafer is controlled to match with a resistivity, so as to realize that a conductive type of the silicon substrate does not change after a device is manufactured, and that the silicon substrate has a high resistivity. The oxygen concentration and the resistivity in silicon crystal can be adjusted separately or together; and operation is flexible, and a yield of a high-resistance silicon crystal is greatly improved.
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公开(公告)号：US11955373B2
公开(公告)日：2024-04-09
申请号：US17290395
申请日：2019-09-29
发明人： Xin Ou , Tiangui You , Wenhui Xu , Pengcheng Zheng , Kai Huang , Xi Wang
IPC分类号： H01L21/762 , H01L29/24
CPC分类号： H01L21/76254 , H01L29/24
摘要： The present invention provides a method for preparing a gallium oxide semiconductor structure and a gallium oxide semiconductor structure obtained thereby. The method comprises: providing a gallium oxide single-crystal wafer (1) having an implantation surface (1a) (S1); performing an ion implantation from the implantation surface (1a) into the gallium oxide single-crystal wafer (1), such that implanted ions reach a preset depth and an implantation defect layer (11) is formed at the preset depth (S2); bonding the implantation surface (1a) to a high thermal conductivity substrate (2) to obtain a first composite structure (S3); performing an annealing treatment on the first composite structure such that the gallium oxide single-crystal wafer (1) in the first composite structure is peeled off along the implantation defect layer (11), thereby obtaining a second composite structure and a third composite structure (S4); and performing a surface treatment on the second composite structure to remove a first damaged layer (111), so as to obtain a gallium oxide semiconductor structure comprising a first gallium oxide layer (12) and the high thermal conductivity substrate (2) (S5). In the gallium oxide semiconductor structure formed using the above method, the first gallium oxide layer (12) is integrated with the high thermal conductivity substrate (2) to effectively improve the thermal conductivity of the first gallium oxide layer (12).
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公开(公告)号：US20240004130A1
公开(公告)日：2024-01-04
申请号：US18037088
申请日：2020-12-01
发明人： Haiyang HUANG , Wei Li , Fengyuan Gan , Yi Zhou
IPC分类号： G02B6/122
CPC分类号： G02B6/122 , G02B2006/12061
摘要： The present invention relates to a micro-nano structure sensitive to a laser beam in a specific direction, including a substrate, wherein an insulating layer is fixedly disposed on the substrate, the insulating layer is provided with two silicon nanowires parallel to each other and having the same shape and size, lead-out nanowires are arranged at both ends of each of the silicon nanowires and are connected with a potentiometer, and a near-field coupling effect occurs between the silicon nanowires and the substrate when laser light irradiates the silicon nanowires, and one silicon nanowire closer to a laser light source is completely suppressed and the other silicon nanowire farther away from the laser light source maintains brightness. The present invention enables precise detection of a laser signal at a specific angle and non-contact signal transmission in a specific direction.
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公开(公告)号：US20230137599A1
公开(公告)日：2023-05-04
申请号：US17586046
申请日：2022-01-27
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Rongwang DAI , Ziwen WANG , Minghao LI , Hongtao XU , Meng CHEN
IPC分类号： H01L21/324 , C30B29/06 , H01L29/06
摘要： The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon. The present method can optimize the atmosphere for batch annealing to achieve better planarization than the conventional technologies. Specifically, the obtained top silicon layer of the SOI wafer has a surface roughness of less than 4 Å.
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公开(公告)号：US20230133916A1
公开(公告)日：2023-05-04
申请号：US17586254
申请日：2022-01-27
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Rongwang DAI , Ziwen WANG , Minghao LI , Meng CHEN , Hongtao XU
IPC分类号： H01L21/762
摘要： The present application provides a process of surface treatment of a silicon-on-insulator (SOI) wafer comprising: providing a SOI wafer comprising a back substrate, a top silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; conducting a first planarization to a surface of the top silicon layer by conducting a batch annealing process at a first target temperature, and conducting a second planarization to a surface of the top silicon layer by conducting a rapid thermal annealing process at a second target temperature. The present application combines the batch annealing process and the rapid thermal annealing process to optimize the SOI wafer, especially the surface roughness of the SOI wafer. The SOI wafer planarized by the two thermal annealing processes has a good surface roughness of the top silicon layer which satisfies process requirements.
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公开(公告)号：US20230133092A1
公开(公告)日：2023-05-04
申请号：US17586324
申请日：2022-01-27
申请人： Zing Semiconductor Corporation , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
发明人： Xing WEI , Rongwang DAI , Ziwen WANG , Minghao LI , Meng CHEN , Hongtao XU
IPC分类号： H01L21/324 , H01L21/762
摘要： A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.
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公开(公告)号：US20220231224A1
公开(公告)日：2022-07-21
申请号：US17607892
申请日：2019-11-04
发明人： ZHITANG SONG , SANNIAN SONG
摘要： The present disclosure provides a phase change memory and a method for making the same. The phase change memory includes a substrate, a plurality of phase change memory cells, and an isolation material layer. The plurality of phase change memory cells are separately disposed on the substrate, the phase change memory cell sequentially includes, from bottom to top, a first electrode material layer, a first transition material layer, an ovonic threshold switching (OTS) material layer, a second transition material layer, a second electrode material layer, a third transition material layer, a phase change material layer, a fourth transition material layer, and a third electrode material layer; The isolation material layer is disposed on the substrate and surrounds side surfaces of the phase change memory cell, and the plurality of phase change memory cells are isolated from each other by isolation material layer.
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公开(公告)号：US20220181200A1
公开(公告)日：2022-06-09
申请号：US17191683
申请日：2021-03-03
申请人： Zing Semiconductor Corporation , SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCES
发明人： Xing WEI , Nan GAO , Zhongying XUE
IPC分类号： H01L21/762
摘要： The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.
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公开(公告)号：US11336250B2
公开(公告)日：2022-05-17
申请号：US17279847
申请日：2017-07-10
发明人： Xin Ou , Kai Huang , Qi Jia , Shibin Zhang , Tiangui You , Xi Wang
摘要： A method for preparing a film bulk acoustic wave device by using a film transfer technology includes: 1) providing an oxide monocrystal substrate; 2) implanting ions from the implantation surface into the oxide monocrystal substrate, and then forming a lower electrode on the implantation surface; or vice versa; and forming a defect layer at the preset depth; 3) providing a support substrate and bonding a structure obtained in step 2) with the support substrate; 4) removing part of the oxide monocrystal substrate along the defect layer so as to obtain an oxide monocrystal film, and transferring the obtained oxide monocrystal film and the lower electrode to the support substrate; 5) etching the support substrate from a bottom of the support substrate to form a cavity; 6) forming an upper electrode on the surface of the oxide monocrystal film.
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