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公开(公告)号：US12132121B2
公开(公告)日：2024-10-29
申请号：US18107559
申请日：2023-02-09
IPC分类号： H01L29/786 , H01L29/04 , H01L29/24
CPC分类号： H01L29/78696 , H01L29/045 , H01L29/24 , H01L29/786 , H01L29/7869 , H01L29/78693
摘要： Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
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公开(公告)号：US20240355934A1
公开(公告)日：2024-10-24
申请号：US18304659
申请日：2023-04-21
申请人： Intel Corporation
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/66969 , H01L29/0847 , H01L29/24
摘要： Described herein are transistors with monolayer transition metal dichalcogenides (TMD) semiconductor material. TMD materials include combination of a transition metal (e.g., molybdenum or tungsten) and a chalcogen (e.g., sulfur or selenium) in a monolayer having a hexagonal crystal structure. A transistor has a single layer of TMD forming a channel region, and multiple layers of the TMD material at the source and drain regions. Upper portions of the multilayer TMD source and drain regions are doped, and conductive contacts are formed over the doped portions.
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3.发明公开公开(公告)号：US20240352619A1
公开(公告)日：2024-10-24
申请号：US18685510
申请日：2021-09-03
申请人： Mitsubishi Electric Corporation , NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY
发明人： Yohei YUDA , Tatsuro WATAHIKI , Yoshinao KUMAGAI , Ken GOTO
IPC分类号： C30B25/10 , H01L29/04 , H01L29/24 , H01L29/812
CPC分类号： C30B25/10 , H01L29/045 , H01L29/24 , H01L29/812
摘要： An object is to provide a technique capable of increasing device characteristics. A crystal lamination structure includes a Ga2O3 single-crystal substrate having a first main surface. The crystal lamination structure includes a Ga2O3 single-crystal layer as an epitaxial growth layer provided on the first main surface of the Ga2O3 single-crystal substrate and having a second main surface on a side opposite to the Ga2O3 single-crystal substrate. A plane direction of the first main surface of the Ga2O3 single-crystal substrate is plane. A plane direction of the second main surface of the Ga2O3 single-crystal layer is plane.
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公开(公告)号：US20240349508A1
公开(公告)日：2024-10-17
申请号：US18751331
申请日：2024-06-23
摘要： A method of forming a device includes the following steps. A multi-layer stack is formed, wherein the multi-layer stack includes a plurality of dielectric layers and a plurality of first sacrificial layers stacked alternately. A first trench is formed in the multi-layer stack. A memory material layer is formed on a sidewall of the first trench. A channel layer is conformally on the sidewall of the first trench and over the memory material layer. A plurality of conductive pillars are formed in the first trench.
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5.发明公开公开(公告)号：US20240339543A1
公开(公告)日：2024-10-10
申请号：US18743686
申请日：2024-06-14
发明人： Witold Kula , Gurtej S. Sandhu , John A. Smythe
IPC分类号： H01L29/786 , H01L21/02 , H01L29/24 , H01L29/66 , H10B99/00
CPC分类号： H01L29/78642 , H01L21/02178 , H01L21/02488 , H01L21/02568 , H01L29/24 , H01L29/66969 , H01L29/78645 , H01L29/78696 , H10B99/00 , H01L21/0262
摘要： An apparatus including an array of memory cells comprising transistors is disclosed. One or more of the transistors comprise a crystalline material extending substantially transverse to a base material. A gate dielectric material is adjacent to the crystalline material. A two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. The gate dielectric material overlies additional portions of the two-dimensional material of the channel region. One or more gates are adjacent to the gate dielectric material. An electronic device is also disclosed comprising one or more of the transistors. The one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. The channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.
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公开(公告)号：US12113074B2
公开(公告)日：2024-10-08
申请号：US18231830
申请日：2023-08-09
发明人： Shunpei Yamazaki
CPC分类号： H01L27/1225 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1266 , H01L29/1033 , H01L29/24 , H01L29/66742 , H01L29/66969 , H01L29/78606 , H01L29/7869
摘要： A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.
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公开(公告)号：US12112946B2
公开(公告)日：2024-10-08
申请号：US17677005
申请日：2022-02-22
申请人： IMEC VZW
发明人： Yuanyuan Shi , Benjamin Groven , Matty Caymax
IPC分类号： H01L21/02 , H01L21/465 , H01L29/24 , H01L29/66
CPC分类号： H01L21/0262 , H01L21/02568 , H01L21/02598 , H01L21/02645 , H01L21/465 , H01L29/66969 , H01L21/0242 , H01L29/24
摘要： A method for providing a film of one or more monolayers of transition metal dichalcogenides on a substrate is disclosed. The method includes providing a substrate; depositing at least one monolayer of the transition metal dichalcogenides on the substrate; and selectively removing superficial islands on top of the at least one monolayer by thermal etching.
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公开(公告)号：US20240332017A1
公开(公告)日：2024-10-03
申请号：US18579031
申请日：2022-07-14
发明人： William SCHEIDELER , Andrew HAMLIN
IPC分类号： H01L21/02 , H01L29/24 , H01L29/66 , H01L29/786
CPC分类号： H01L21/02623 , H01L21/02565 , H01L29/24 , H01L29/66969 , H01L29/7869
摘要： In a liquid printing method, a second workpiece is applied onto a first workpiece. A metal on the second workpiece contacts a dielectric on the first workpiece thereby forming an alloyed oxide film. This can be used to form a liquid metal printed 2D alloyed oxide film transistor. The alloyed oxide film can be InOx or other materials.
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公开(公告)号：US12106729B2
公开(公告)日：2024-10-01
申请号：US18132554
申请日：2023-04-10
发明人： Susumu Kawashima , Naoto Kusumoto
IPC分类号： G09G3/36 , G02F1/1362 , G02F1/1368 , G09G3/3225 , G09G3/3266 , G09G3/3275 , G09G3/34 , H01L27/12 , H01L29/24 , H01L29/786 , H04N23/57 , H10K59/121 , H10K59/131 , H10K59/65
CPC分类号： G09G3/3688 , G02F1/136213 , G02F1/13624 , G02F1/1368 , G09G3/3225 , G09G3/3266 , G09G3/3275 , G09G3/3413 , G09G3/3677 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/24 , H01L29/7869 , H10K59/1213 , H10K59/1216 , H10K59/131 , H10K59/65 , G09G2300/0426 , G09G2300/0439 , G09G2300/0809 , G09G2320/0233 , G09G2320/0252 , G09G2330/021 , H04N23/57
摘要： A display device capable of improving image quality is provided. The display device includes a first circuit, a pixel, and a wiring. The first circuit has a function of supplying data to the wiring and a function of making the wiring floating to hold the data. The pixel has a function of taking in the data twice from the wiring and performing addition. The pixel can perform the first writing of the data in a period during which the data is supplied to the wiring, and can perform the second writing of the data in a period during which the data is held in the wiring. Therefore, by one lime of data charging to a source line, a data potential larger than or equal to an output voltage of a source driver can be supplied to a display element.
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公开(公告)号：US12101946B2
公开(公告)日：2024-09-24
申请号：US18387921
申请日：2023-11-08
发明人： Kamal M. Karda , Yi Fang Lee , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Ramanathan Gandhi , Karthik Sarpatwari , Scott E. Sills , Sameer Chhajed
IPC分类号： H10B99/00 , H01L27/092 , H01L27/12 , H01L29/24 , H01L29/267 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H10B99/00 , H01L27/092 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1259 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/66969 , H01L29/78642 , H01L29/7869
摘要： Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
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