公开(公告)号：US20040196108A1

公开(公告)日：2004-10-07

申请号：US10737532

申请日：2003-12-16

Applicant: STMicroelectronics Belgium N.V.

Inventor： Jan Frans Lucien Craninckx

IPC: H03L007/00

CPC classification number: H03L7/081 ,  H03L7/0893 ,  H03L7/1976

Abstract: A Phase-Locked Loop is provided that includes a main loop, a calibration loop, and Control Logic. The main loop comprises, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Voltage Controlled Oscillator and a Frequency Divider. The calibration loop is coupled to the Phase Frequency Detector and comprises a Calibration Charge Pump and a Calibration Loop Filter. The Control Logic controls the Frequency Divider and receives a control input signal. A Reference Frequency Signal is coupled to the Phase Frequency Detector and the Control Logic, and a calibration signal is coupled to the calibration loop. Additionally, the main loop further comprises a delay generator controlled by the Control Logic and arranged to receive correction signals from the calibration loop and to send an output signal to the Phase Frequency Detector.

Abstract translation: 提供了一个锁相环，包括主回路，校准回路和控制逻辑。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，压控振荡器和分频器。 校准环路耦合到相位检波器，包括校准电荷泵和校准环路滤波器。 控制逻辑控制分频器并接收控制输入信号。 参考频率信号耦合到相位频率检测器和控制逻辑，并且校准信号耦合到校准环路。 此外，主回路还包括由控制逻辑控制的延迟发生器，并被布置成从校准环路接收校正信号并向相位检波器发送输出信号。

公开(公告)号：US20040180638A1

公开(公告)日：2004-09-16

申请号：US10718256

申请日：2003-11-20

Applicant: STMicroelectronics Belgium N.V.

Inventor： Jan Frans Lucien Craninckx

IPC: H04B001/18

CPC classification number: H03L7/18 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0996

Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop is coupled to the Phase Frequency Detector, and comprises a Calibration Charge Pump, a Multiplexer and Y Calibration Loop Filters, with Y being an integer. The Control Logic controls the Phase-Switching Fractional Divider and the Multiplexer. A Reference Frequency Signal is coupled to the Phase Frequency Detector and a Calibration Signal is coupled to the calibration loop. The main loop further comprises a Phase-adjusting Block coupled to a Demultiplexer. The Phase-adjusting Block is arranged so as to receive at least one correction signal from the calibration loop.

Abstract translation: 提供了具有多相时钟的锁相环。 锁相环包括主回路，校准回路和控制逻辑。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，多相电压控制振荡器和相位切换分数分频器。 校准环路耦合到相位检波器，并且包括校正电荷泵，多路复用器和Y校准环路滤波器，Y为整数。 控制逻辑控制相位切换分数分频器和多路复用器。 参考频率信号耦合到相位频率检测器，校准信号耦合到校准环路。 主环路还包括耦合到解复用器的相位调整块。 相位调整块被布置成从校准环路接收至少一个校正信号。

公开(公告)号：US20040157577A1

公开(公告)日：2004-08-12

申请号：US10718257

申请日：2003-11-20

Applicant: STMicroelectronics Belgium N.V.

Inventor： Jan Frans Lucien Craninckx

IPC: H04B001/06 ,  H04B007/00 ,  H03D003/24

CPC classification number: H03L7/0996 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and a Multiplexer. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop includes Y Calibration Loop Filters, with Y being an integer, coupled to the Multi-Phase Voltage Controlled Oscillator, and Control Logic for controlling the Phase-Switching Fractional Divider. The Multiplexer is coupled between an output of the Main Charge Pump and inputs of the Main Loop Filter and the Y Calibration Loop Filters. A Reference Frequency Signal is coupled to the Phase Frequency Detector, a control signal from the Control Logic is coupled to the Multiplexer, and a Calibration Signal is coupled to a control input of the Control Logic.

Abstract translation: 提供了具有多相时钟的锁相环。 锁相环包括主回路，校准回路和多路复用器。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，多相电压控制振荡器和相位切换分数分频器。 校准回路包括Y校准环路滤波器，Y为整数，耦合到多相电压控制振荡器，控制逻辑用于控制相位切换分数分频器。 多路复用器连接在主电荷泵的输出端和主回路滤波器和Y校准环路滤波器的输入端之间。 参考频率信号耦合到相位频率检测器，来自控制逻辑的控制信号耦合到多路复用器，校准信号耦合到控制逻辑的控制输入端。