公开(公告)号：US20040180638A1

公开(公告)日：2004-09-16

申请号：US10718256

申请日：2003-11-20

Applicant: STMicroelectronics Belgium N.V.

Inventor： Jan Frans Lucien Craninckx

IPC: H04B001/18

CPC classification number: H03L7/18 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0996

Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop is coupled to the Phase Frequency Detector, and comprises a Calibration Charge Pump, a Multiplexer and Y Calibration Loop Filters, with Y being an integer. The Control Logic controls the Phase-Switching Fractional Divider and the Multiplexer. A Reference Frequency Signal is coupled to the Phase Frequency Detector and a Calibration Signal is coupled to the calibration loop. The main loop further comprises a Phase-adjusting Block coupled to a Demultiplexer. The Phase-adjusting Block is arranged so as to receive at least one correction signal from the calibration loop.

Abstract translation: 提供了具有多相时钟的锁相环。 锁相环包括主回路，校准回路和控制逻辑。 主回路包括串联耦合的相位检波器，主电荷泵，主回路滤波器，多相电压控制振荡器和相位切换分数分频器。 校准环路耦合到相位检波器，并且包括校正电荷泵，多路复用器和Y校准环路滤波器，Y为整数。 控制逻辑控制相位切换分数分频器和多路复用器。 参考频率信号耦合到相位频率检测器，校准信号耦合到校准环路。 主环路还包括耦合到解复用器的相位调整块。 相位调整块被布置成从校准环路接收至少一个校正信号。