公开(公告)号：US07138689B2

公开(公告)日：2006-11-21

申请号：US10740232

申请日：2003-12-18

申请人： Tsuyoshi Inoue ,  Hiroshi Yamamoto ,  Mitsuru Yoshikawa ,  Saiki Hotate

发明人： Tsuyoshi Inoue ,  Hiroshi Yamamoto ,  Mitsuru Yoshikawa ,  Saiki Hotate

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/6656

摘要： A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof. The semiconductor device is formed as a transistor with a configuration having gate insulation film 21 and gate electrode 22 formed on semiconductor substrate 10, inner sidewall insulation film 25 formed at least on part of the gate insulation film and on both sides of the gate electrode, outer sidewall insulation film 26 formed at least on part of the gate insulation film and on both sides of the inner sidewall insulation film, low concentration impurity area 23 containing an impurity at a low concentration and formed in the semiconductor substrate in the area underneath the inner sidewall insulation film and the outer sidewall insulation film, and high concentration impurity area 27 containing an impurity at a concentration higher than the low concentration impurity area and formed in the semiconductor substrate in the area underneath both sides of the outer sidewall insulation film.

摘要翻译： 具有具有双层侧壁绝缘膜的具有高击穿电压的MOS晶体管的半导体衬底，并且可以抑制对其电特性及其方法的负面影响。 半导体器件形成为具有形成在半导体衬底10上的栅极绝缘膜21和栅电极22，栅极绝缘膜的至少一部分和栅电极的两侧上形成的内侧壁绝缘膜25的晶体管， 外侧壁绝缘膜26形成在栅极绝缘膜的至少一部分上以及内侧壁绝缘膜的两侧，低浓度杂质区23含有低浓度的杂质，并形成在半导体衬底内的内部区域 侧壁绝缘膜和外侧壁绝缘膜，以及高浓度杂质区域27，其含有浓度高于低浓度杂质区域的杂质，并且形成在半导体衬底中在外侧壁绝缘膜的两侧下方的区域中。