摘要:
A baud rate generator includes a first counter, a timer and a baud rate correcting circuit. The first counter is configured to count bits of an inputted serial data. The timer is configured to measure a time for which the first counter counts a predetermined number of bits based on a reference clock signal. The baud rate correcting circuit is configured to output a baud rate correction value based on the measurement time by the timer such that a baud rate in a serial communication is corrected based on the baud rate correction value.
摘要:
There is provided an address decoding circuit including (a) a first address decoder for practical use for decoding an address which is particular to an individual object, (b) a second address decoder for test use for decoding a constant address regardless of objects, and (c) a logic circuit receiving a selection signal and switching from decoding result transmitted thereto from the first address decoder to decoding result transmitted thereto from the second address decoder, and vice versa in accordance with the selection signal. The address decoding circuit selects decoding result of an address used for a test, which is particular to peripheral macros, in a test mode in accordance with the selection signal. Hence, when peripheral macros are mounted on different chips, it would be possible to use a common vector, even if an address for practical use is changed. This ensures reduction in steps of re-constructing test vector.
摘要:
A baud rate generator includes a first counter, a timer and a baud rate correcting circuit. The first counter is configured to count bits of an inputted serial data. The timer is configured to measure a time for which the first counter counts a predetermined number of bits based on a reference clock signal. The baud rate correcting circuit is configured to output a baud rate correction value based on the measurement time by the timer such that a baud rate in a serial communication is corrected based on the baud rate correction value.
摘要:
A data processor includes a CPU and an A/D converter for converting one of several analog inputs into digital data. A data memory stores data designating analog inputs to be converted. A circuit, responsive to an A/D conversion completion signal from the A/D converter, supplies a macro service operation request to the CPU, which interrupts the CPU without having to save the contents of a CPU program counter and a CPU status register. Upon completion of the A/D conversion, the converted digital data are stored in a predetermined location, and CPU execution resumes.
摘要:
In a microcomputer including a processor, a data memory and a controller for controlling the processor and the data memory, the data memory includes a adaptivity degree data group indicative of the adaptivity degree to the fuzzy set, and an area for storing the result of processing. The processor includes an adaptivity degree data pointer, a result store area pointer, a conformity degree data storing register, and a processing number count register. The microcomputer internally includes a fuzzy inference exclusive-instruction, which causes to compare data in the conformity degree data storing register with data designated by the adaptivity degree data pointer, so as to select a smaller one, and compare the selected dam with data designated by the result store area pointer, so as to store a large one at the area for storing the result of processing, designated by the the result store area pointer. The above processings are repealed the number of processing in the processing number count register, while updating the result store area pointer and the adaptivity degree data group pointer.
摘要:
An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.