公开(公告)号：US20110024859A1

公开(公告)日：2011-02-03

申请号：US12937013

申请日：2009-03-30

申请人： Kenichi Miyazaki ,  Osamu Matsushima ,  Shigeru Niki ,  Keiichiro Sakurai ,  Shogo Ishizuka

发明人： Kenichi Miyazaki ,  Osamu Matsushima ,  Shigeru Niki ,  Keiichiro Sakurai ,  Shogo Ishizuka

IPC分类号： H01L31/0232 ,  H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14645 ,  H01L31/0322

摘要： A photoelectric conversion device has a high S/N ratio and can increase the detection efficiency even under a low luminance. The photoelectric conversion device generates an increased electric charge by impact ionization in a photoelectric conversion unit formed from a chalcopyrite type semiconductor, so as to improve dark current characteristic. The photoelectric conversion device includes: a lower electrode layer; a compound semiconductor thin film of chalcopyrite structure disposed on the lower electrode layer and having a high resistivity layer on a surface; and a transparent electrode layer disposed on the compound semiconductor thin film, wherein the lower electrode layer, the compound semiconductor thin film, and the transparent electrode layer are laminated one after another, and a reverse bias voltage is applied between the transparent electrode layer and the lower electrode layer, and the multiplication by the impact ionization of the electric charge generated by photoelectric conversion is generated within the compound semiconductor thin film. It is also possible to provide a fabrication method for such photoelectric conversion device, and a solid state imaging device using the photoelectric conversion device.

摘要翻译： 光电转换装置的S / N比高，即使在低亮度下也能够提高检测效率。 光电转换装置通过由黄铜矿型半导体形成的光电转换单元中的冲击电离产生增加的电荷，从而改善暗电流特性。 光电转换装置包括：下电极层; 黄铜矿结构的化合物半导体薄膜设置在下电极层上并且在表面上具有高电阻率层; 以及设置在化合物半导体薄膜上的透明电极层，其中下电极层，化合物半导体薄膜和透明电极层依次层叠，并且在透明电极层和透明电极层之间施加反向偏置电压 并且在化合物半导体薄膜内产生通过光电转换产生的电荷的冲击电离的乘积。 也可以提供这种光电转换装置的制造方法和使用该光电转换装置的固态成像装置。

公开(公告)号：US20100295145A1

公开(公告)日：2010-11-25

申请号：US12781850

申请日：2010-05-18

申请人： Kenichi Miyazaki ,  Osamu Matsushima

发明人： Kenichi Miyazaki ,  Osamu Matsushima

IPC分类号： H01L31/105 ,  H01L31/18 ,  H01L31/0264

CPC分类号： H01L31/0322 ,  H01L31/0336 ,  H01L31/105 ,  H01L31/109 ,  Y02E10/541

摘要： A light-absorbing layer is composed of a compound-semiconductor film of charcopyrite structure, a surface layer is disposed on the light-absorbing layer, the surface layer having a higher band gap energy than the compound-semiconductor film, an upper electrode layer is disposed on the surface layer, and a lower electrode layer is disposed on a backside of the light-absorbing layer in opposition to the upper electrode layer, the upper electrode layer and the lower electrode layer having a reverse bias voltage applied in between to detect electric charges produced by photoelectric conversion in the compound-semiconductor film, as electric charges due to photoelectric conversion are multiplied by impact ionization, while the multiplication by impact ionization of electric charges is induced by application of a high-intensity electric field to a semiconductor of charcopyrite structure, allowing for an improved dark-current property, and an enhanced efficiency even in detection of low illumination intensities, with an enhanced S/N ratio.

摘要翻译： 光吸收层由正铁矿结构的化合物半导体膜构成，表面层设置在光吸收层上，表面层具有比化合物半导体膜更高的带隙能量，上电极层为 配置在表面层上，下电极层设置在与上电极层相对的光吸收层的背面，上电极层和下电极层之间施加反向偏压，以检测电 在化合物半导体膜中通过光电转换产生的电荷由于光电转换而产生的电荷乘以冲击电离，而电荷的冲击电离的乘积是通过向高锰酸盐半导体施加高强度电场而引起的 结构，允许改善的暗电流特性，以及即使在低光的检测中也提高了效率 内生强度，S / N比提高。

公开(公告)号：US06402011B1

公开(公告)日：2002-06-11

申请号：US09633293

申请日：2000-08-04

申请人： Masahiro Taniguchi ,  Kazumi Ishimoto ,  Koichi Nagai ,  Osamu Yamazaki ,  Tatsuaki Kitagawa ,  Osamu Matsushima ,  Kazuhiro Uji ,  Seizo Nemoto

发明人： Masahiro Taniguchi ,  Kazumi Ishimoto ,  Koichi Nagai ,  Osamu Yamazaki ,  Tatsuaki Kitagawa ,  Osamu Matsushima ,  Kazuhiro Uji ,  Seizo Nemoto

IPC分类号： B23K3102

CPC分类号： B23K3/085 ,  B23K1/008 ,  B23K2101/42 ,  H05K3/3415 ,  H05K3/3447 ,  H05K3/3494 ,  H05K2203/087 ,  H05K2203/304

摘要： For reflow soldering, radiant heating is applied to one surface of a printed circuit board on which electronic components are placed and onto which cream solder is supplied and at the same time hot air is blown locally and roughly perpendicular to to-be-connected points on said one surface of the printed circuit board. This reflow method permits secure soldering even if the hot air is set at a temperature not exceeding the heat resistance of the electronic components, which is possilbe because of its combination with the radiant heat. Moreover, this reflow method can permit soldering in such a manner that only the to-be-connected points are heated selectively, because the hot air is blown locally and roughly perpendicular to the points to be connected. Thus, this reflow method prevents heat damage to other sections than the to-be-connected points and ensures that the solder at the to-be-connected points is melted.

摘要翻译： 对于回流焊接，辐射加热被施加到印刷电路板的放置电子部件的一个表面上，并且在其上供应奶油焊膏，并且同时热空气局部地被吹送并大致垂直于待连接点 所述印刷电路板的一个表面。 这种回流方法即使热空气被设定在不超过电子部件的耐热性的温度下，由于与辐射热的组合，所以能够进行安全的焊接。 此外，这种回流方法可以以这样的方式允许焊接，即只有待连接点被选择性地加热，因为热空气局部地吹动并且大致垂直于要连接的点。 因此，这种回流方法可防止对待连接点的其他部分的热损伤，并确保待连接点处的焊料熔化。

公开(公告)号：US5649219A

公开(公告)日：1997-07-15

申请号：US708884

申请日：1996-09-04

申请人： Osamu Matsushima

发明人： Osamu Matsushima

IPC分类号： G06F15/78 ,  G06F11/26 ,  G06F11/273 ,  G06F11/00

CPC分类号： G06F11/261 ,  G06F11/2733

摘要： In a microcomputer with built-in SOG region system debugging is made possible using a gate array provided outside the microcomputer by supplying signals transferred between a CPU and the gate array to external terminals used for transferring signals between the interior of the microcomputer and a peripheral device outside the microcomputer. In order to supply necessary signals to the gate array connected to the external terminals, a selection circuit which outputs signals between CPU and the SOG region to the external terminals by means of a mode switching signal is provided. By the provision of the selection circuit, it becomes possible to output the signals between the CPU and the SOG region to the external terminals by switching, and to transmit the signals of CPU to the gate array provided outside the microcomputer. Accordingly, it becomes possible to debug the system using the gate array provided outside the microcomputer.

摘要翻译： 在具有内置SOG区域的微型计算机中，通过将在CPU和门阵列之间传送的信号提供给外部终端，用于在微计算机的内部和外围设备之间传送信号，使用在微计算机外部提供的门阵列可以进行调试 在微机外 为了向连接到外部端子的门阵列提供必要的信号，提供了通过模式切换信号将CPU和SOG区域之间的信号输出到外部端子的选择电路。 通过提供选择电路，可以通过切换将CPU和SOG区域之间的信号输出到外部端子，并将CPU的信号发送到设置在微型计算机外部的门阵列。 因此，可以使用设置在微计算机外部的门阵列来调试系统。

公开(公告)号：US5208781A

公开(公告)日：1993-05-04

申请号：US704157

申请日：1991-05-22

申请人： Osamu Matsushima

发明人： Osamu Matsushima

IPC分类号： G11C11/41 ,  G06F1/32 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F1/3215 ,  G06F1/3275 ,  Y02B60/1225 ,  Y02B60/1228

摘要： A memory device includes a memory, an address latch, a built-in incrementer, and an address decoder. The address decoder has a mapping register which assigns the memory to a predetermined address. The address decoder further includes a standby signal producer which detects whether or not the address latch addresses an address specified by the mapping register and which sets the memory device to a standby state of a low power consumption when such is not detected. The memory device can be set to a standby state even when the memory device is connected to a microcomputer with a protocol by which an address of the memory is not outputted each time. This arrangement enables to save power consumption of the computer, to decrease the load of a power supply circuit in a microcomputer applied apparatus and to make the apparatus compact.

公开(公告)号：US06941200B2

公开(公告)日：2005-09-06

申请号：US10398547

申请日：2001-10-15

申请人： Osamu Sonoyama ,  Takahiro Yokomae ,  Yoichi Sugitomo ,  Masahide Yoshihara ,  Osamu Matsushima ,  Toyotoshi Tsujikawa ,  Takeshi Asano ,  Hitoshi Kubota

发明人： Osamu Sonoyama ,  Takahiro Yokomae ,  Yoichi Sugitomo ,  Masahide Yoshihara ,  Osamu Matsushima ,  Toyotoshi Tsujikawa ,  Takeshi Asano ,  Hitoshi Kubota

IPC分类号： B61B13/00 ,  G05D1/02 ,  G01C22/00

CPC分类号： G05D1/0297 ,  G05D1/0272 ,  G05D1/0274 ,  G05D1/0282 ,  G05D2201/0216

摘要： A waiting time of an automated guided vehicle is substantially eliminated by significantly shortening the communication time of various information, and the transport efficiency of an automated guided vehicle as well as the operating rate of work stations and production lines as a whole are improved, and in addition, the flexibility of an operation control system for the automated guided vehicle is improved. An automated guided vehicle (1) includes a wireless local area network adapter (11) for passing information by radio with an operation control unit connected to the local area network or with another automated guided vehicle, a memory part (12) for storing at least information from the operation control unit or from another automated guided vehicle and information related to the automated guided vehicle itself, and a control part (14) for controlling the wireless local area network adapter and the memory part.

摘要翻译： 通过显着缩短各种信息的通信时间，自动化引导车的等待时间得到了实质性的消除，自动化引导车辆的运输效率以及整个工作站和生产线的运行率得到了改善，并且在 此外，提高了自动导引车辆的操作控制系统的灵活性。 一种自动导引车辆（1）包括无线局域网适配器（11），用于通过无线电与通过连接到局域网或与其他自动导引车辆的操作控制单元传递信息，存储部分（12）至少存储 来自操作控制单元或来自另一自动引导车辆的信息以及与自动引导车辆本身相关的信息，以及用于控制无线局域网适配器和存储器部分的控制部分（14）。

公开(公告)号：US5331571A

公开(公告)日：1994-07-19

申请号：US919417

申请日：1992-07-22

申请人： Alan P. Aronoff ,  Marc S. Birnkrant ,  Osamu Matsushima ,  Kyosuke Sugishita ,  Hisaharu Oba ,  Katta N. Reddy ,  Richard I. Olsen ,  Brent N. Dichter

发明人： Alan P. Aronoff ,  Marc S. Birnkrant ,  Osamu Matsushima ,  Kyosuke Sugishita ,  Hisaharu Oba ,  Katta N. Reddy ,  Richard I. Olsen ,  Brent N. Dichter

IPC分类号： G06F11/26 ,  G06F11/267 ,  G06G7/48 ,  G06F15/00

CPC分类号： G06F11/261 ,  G06F11/2236

摘要： An architecture is provided for testing and emulating an integrated circuit with embedded function blocks. The output nodes of the function blocks are connected through a tri-state buffer to a test bus which in turn is connected to configurable external pins. The external pins multiplex the normal I/O in normal mode and the test bus I/O in the test mode. The test bus is also connected through multiplexers to input nodes of function blocks. In test mode, the function block nodes are accessed through the test bus. For emulation of an embedded microcontroller or microprocessor, the internal connections of the microcontroller (or microprocessor) are brought out to those external pins which in normal operation are connected only to the microcontroller and not to any other function block. An in-circuit emulator (ICE) emulating the microcontroller is connected to the other function blocks through those external pins.

摘要翻译： 提供了一种用于测试和仿真具有嵌入式功能块的集成电路的架构。 功能块的输出节点通过三态缓冲器连接到测试总线，测试总线又连接到可配置的外部引脚。 外部引脚在正常模式下复用正常I / O，并在测试模式下复用测试总线I / O。 测试总线也通过多路复用器连接到功能块的输入节点。 在测试模式下，通过测试总线访问功能块节点。 为了仿真嵌入式微控制器或微处理器，微控制器（或微处理器）的内部连接被引出到正常操作中仅连接到微控制器而不是任何其他功能块的那些外部引脚。 仿真微控制器的在线仿真器（ICE）通过这些外部引脚连接到其他功能块。

公开(公告)号：US08378444B2

公开(公告)日：2013-02-19

申请号：US12781850

申请日：2010-05-18

申请人： Kenichi Miyazaki ,  Osamu Matsushima

发明人： Kenichi Miyazaki ,  Osamu Matsushima

IPC分类号： H01L29/76

CPC分类号： H01L31/0322 ,  H01L31/0336 ,  H01L31/105 ,  H01L31/109 ,  Y02E10/541

摘要： A light-absorbing layer is composed of a compound-semiconductor film of chalcopyrite structure, a surface layer is disposed on the light-absorbing layer, the surface layer having a higher band gap energy than the compound-semiconductor film, an upper electrode layer is disposed on the surface layer, and a lower electrode layer is disposed on a backside of the light-absorbing layer in opposition to the upper electrode layer, the upper electrode layer and the lower electrode layer having a reverse bias voltage applied in between to detect electric charges produced by photoelectric conversion in the compound-semiconductor film, as electric charges due to photoelectric conversion are multiplied by impact ionization, while the multiplication by impact ionization of electric charges is induced by application of a high-intensity electric field to a semiconductor of chalcopyrite structure, allowing for an improved dark-current property, and an enhanced efficiency even in detection of low illumination intensities, with an enhanced S/N ratio.

摘要翻译： 光吸收层由黄铜矿结构的化合物半导体膜构成，表面层设置在光吸收层上，表面层具有比化合物半导体膜更高的带隙能量，上电极层为 配置在表面层上，下电极层设置在与上电极层相对的光吸收层的背面，上电极层和下电极层之间施加反向偏压，以检测电 在化合物半导体膜中，通过光电转换产生的电荷产生的电荷乘以冲击电离，而通过对黄铜矿的半导体施加高强度电场而引起电荷的冲击电离的乘积 结构，允许改善的暗电流特性，以及即使在低光的检测中也提高了效率 内生强度，S / N比提高。

公开(公告)号：US20100243057A1

公开(公告)日：2010-09-30

申请号：US12730211

申请日：2010-03-23

申请人： Goro NAKATANI ,  Osamu Matsushima ,  Takamitsu Yamanaka

发明人： Goro NAKATANI ,  Osamu Matsushima ,  Takamitsu Yamanaka

IPC分类号： H01L31/00 ,  H01L31/0264 ,  H01L31/18 ,  H01L31/12

CPC分类号： H01L31/0322 ,  H01L27/14632 ,  H01L27/14687 ,  H01L31/072 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

摘要： The semiconductor device according to the present invention includes: a semiconductor substrate; an integrated circuit formed on the semiconductor substrate; and a photoelectric converter, stacked on the integrated circuit, having a light absorbing layer made of a compound semiconductor having a chalcopyrite structure.

摘要翻译： 根据本发明的半导体器件包括：半导体衬底; 形成在所述半导体基板上的集成电路; 以及堆叠在集成电路上的具有由具有黄铜矿结构的化合物半导体制成的光吸收层的光电转换器。

公开(公告)号：US6145734A

公开(公告)日：2000-11-14

申请号：US835989

申请日：1997-04-11

申请人： Masahiro Taniguchi ,  Kazumi Ishimoto ,  Koichi Nagai ,  Osamu Yamazaki ,  Tatsuaki Kitagawa ,  Osamu Matsushima ,  Kazuhiro Uji ,  Seizo Nemoto

发明人： Masahiro Taniguchi ,  Kazumi Ishimoto ,  Koichi Nagai ,  Osamu Yamazaki ,  Tatsuaki Kitagawa ,  Osamu Matsushima ,  Kazuhiro Uji ,  Seizo Nemoto

IPC分类号： B23K1/008 ,  B23K3/08 ,  H05K3/34 ,  B23K1/005 ,  B23K1/012

CPC分类号： B23K3/085 ,  B23K1/008 ,  H05K3/3494 ,  B23K2201/42 ,  H05K2203/087 ,  H05K2203/304 ,  H05K3/3415 ,  H05K3/3447

摘要： For reflow soldering, radiant heating is applied to one surface of a printed circuit board on which electronic components are placed and onto which cream solder is supplied and at the same time hot air is blown locally and roughly perpendicular to to-be-connected points on said one surface of the printed circuit board. This reflow method permits secure soldering even if the hot air is set at a temperature not exceeding the heat resistance of the electronic components, which is possilbe because of its combination with the radiant heat. Moreover, this reflow method can permit soldering in such a manner that only the to-be-connected points are heated selectively, because the hot air is blown locally and roughly perpendicular to the points to be connected. Thus, this reflow method prevents heat damage to other sections than the to-be-connected points and ensures that the solder at the to-be-connected points is melted.