公开(公告)号：US07423315B2

公开(公告)日：2008-09-09

申请号：US11265208

申请日：2005-11-03

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

IPC分类号： H01L29/36

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/7811

摘要： The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

摘要翻译： 本申请提供了一种半导体器件，其包括第一导电型半导体衬底，形成在第一导电型半导体衬底上的柱结构部分，并且由平行于第一导电型主要表面的一个方向排列的五个半导体柱层 以及形成在第一导电型半导体基板上并将柱结构部分夹在隔离绝缘部分之间的隔离绝缘部分，其中柱结构部分由第一第一导电型柱层，第二第一导电型支柱层， 导电型柱层和夹着第一第一导电型柱层的第三第一导电型柱层，设置在第一第一导电型柱层和第二第一导电型柱之间的第一第二导电型柱层 层和第二第二导电类型 柱层，设置在第一第一导电型柱层和第三第一导电型柱层之间。

公开(公告)号：US20050253190A1

公开(公告)日：2005-11-17

申请号：US11101570

申请日：2005-04-08

申请人： Hideki Okumura ,  Mitsuhiko Kitagawa ,  Takuma Hara ,  Takayoshi Ino ,  Kiyotaka Arai ,  Satoshi Taji ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Mitsuhiko Kitagawa ,  Takuma Hara ,  Takayoshi Ino ,  Kiyotaka Arai ,  Satoshi Taji ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368

摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer provided on the surface of the semiconductor substrate; a base layer provided on the surface of the semiconductor layer; a source layer provided on the surface of the base layer; a trench formed to pass through the source layer, the base layer, and the semiconductor layer from the surface of the source layer, and reaching the semiconductor substrate; a gate electrode provided from the source layer to at least the semiconductor layer within the trench; and an insulator provided between the gate electrode and the base layer so as to fill in the inside of the trench below the gate electrode, the insulator insulating the gate electrode from the base layer, and generating a potential distribution from the gate electrode toward the semiconductor substrate when a voltage is applied to the gate electrode.

摘要翻译： 半导体器件包括半导体衬底; 设置在所述半导体衬底的表面上的半导体层; 设置在所述半导体层的表面上的基底层; 源层，设置在基层的表面上; 形成为从源极层的表面通过源极层，基极层和半导体层并到达半导体基板的沟槽; 从所述源极层至所述沟槽内的所述半导体层设置的栅电极; 以及设置在所述栅电极和所述基极层之间的绝缘体，以便填充所述栅电极下方的所述沟槽的内部，所述绝缘体将所述栅电极与所述基极层绝缘，并且从所述栅电极向所述半导体产生电势分布 衬底，当电压施加到栅电极时。

公开(公告)号：US20060108600A1

公开(公告)日：2006-05-25

申请号：US11265208

申请日：2005-11-03

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Satoshi Aida ,  Shigeo Kouzuki ,  Masaru Izumisawa ,  Satoshi Taji ,  Kenichi Tokano

IPC分类号： H01L29/423

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/7811

摘要： The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

摘要翻译： 本申请提供了一种半导体器件，其包括第一导电型半导体衬底，形成在第一导电型半导体衬底上的柱结构部分，并且由平行于第一导电型主要表面的一个方向排列的五个半导体柱层 以及形成在第一导电型半导体基板上并将柱结构部分夹在隔离绝缘部分之间的隔离绝缘部分，其中柱结构部分由第一第一导电型柱层，第二第一导电型支柱层， 导电型柱层和夹着第一第一导电型柱层的第三第一导电型柱层，设置在第一第一导电型柱层和第二第一导电型柱之间的第一第二导电型柱层 层和第二第二导电类型 柱层，设置在第一第一导电型柱层和第三第一导电型柱层之间。