利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.028 秒)

    Semiconductor device and method for manufacturing the same
    1.
    发明授权
    Semiconductor device and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US08415711B2

    公开(公告)日：2013-04-09

    申请号：US13234061

    申请日：2011-09-15

    申请人： Mitsuhiko Kitagawa

    发明人： Mitsuhiko Kitagawa

    IPC分类号： H01L29/66

    CPC分类号： H01L29/1095 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66704 ,  H01L29/7393 ,  H01L29/7821 ,  H01L29/7825

    摘要： According to an embodiment, a semiconductor device includes a first trench being provided in an N+ substrate. An N layer, an N− layer, a P layer, and an N+ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P+ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.

    摘要翻译： 根据实施例，半导体器件包括设置在N +衬底中的第一沟槽。 以堆叠的方式形成N层，N层，P层和N +层以覆盖第一沟槽。 半导体器件包括第二和第三沟槽。 形成P +层以覆盖第二沟槽。 沟槽栅形成为覆盖第三沟槽。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20080315343A1

    公开(公告)日：2008-12-25

    申请号：US12030674

    申请日：2008-02-13

    申请人： Mitsuhiko Kitagawa

    发明人： Mitsuhiko Kitagawa

    IPC分类号： H01L29/06

    CPC分类号： H01L29/861 ,  H01L21/84 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/785 ,  H01L29/8611 ,  H01L33/34

    摘要： A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.

    摘要翻译： 一种半导体器件包括：第一绝缘层; 设置在所述第一绝缘层上的半导体层; 选择性地设置在所述半导体层中的第一半导体区域; 选择性地设置在所述半导体层中并与所述第一半导体区隔开的第二半导体区域; 设置成与所述第一半导体区域接触的第一主电极; 设置成与第二半导体区域接触的第二主电极; 设置在所述半导体层上的第二绝缘层; 设置在位于所述第一半导体区域和所述第二半导体区域之间的所述半导体层的部分上方的所述第二绝缘层中的第一导电材料; 以及设置在与所述第一导电材料相对的所述半导体层的与所述第一导电材料相接触并且到达所述第一绝缘层的部分中的沟槽中的第二导电材料。

    Field effect transistor and application device thereof
    4.
    发明授权
    Field effect transistor and application device thereof 有权
    场效应晶体管及其应用器件

    公开(公告)号：US07385255B2

    公开(公告)日：2008-06-10

    申请号：US11250058

    申请日：2005-10-12

    申请人： Mitsuhiko Kitagawa ,  Yoshiaki Aizawa

    发明人： Mitsuhiko Kitagawa ,  Yoshiaki Aizawa

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7801 ,  H01L25/167 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7825 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 or by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.

    摘要翻译： 本发明提供具有低导通电阻和高耐受电压以及小的输出电容（C（gd）等）的MOSFET。 MOSFET具有在p型基极层4的表面上有选择地形成的p型基极层4和n型源极层5。 n型漏极层7形成在离开p型基极层4的位置。 在p型基极层4和n型漏极层7之间的区域的表面上，n型漂移半导体层12和p型漂移半导体层13从p型基极层 4到n型漏极层7。 此外，在n型源极层5和n型漏极层7之间的区域中，通过栅极绝缘膜14形成栅电极15。 利用该结构，栅电极的相邻区域在n型漂移半导体层12和p型漂移半导体层13之间的内置电位或栅电极的电位耗尽， 源电极和漏电极为0电位。

    Transistor
    5.
    发明申请
    Transistor 失效

    公开(公告)号：US20060231894A1

    公开(公告)日：2006-10-19

    申请号：US11405672

    申请日：2006-04-18

    申请人： Mitsuhiko Kitagawa ,  Takashi Nishimura ,  Yusuke Kawaguchi ,  Syotaro Ono

    发明人： Mitsuhiko Kitagawa ,  Takashi Nishimura ,  Yusuke Kawaguchi ,  Syotaro Ono

    IPC分类号： H01L27/12

    CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4933 ,  H01L29/7397 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78624

    摘要： A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of the first conductivity type, and a base region of the second conductivity type provided between the source portion and the drain portion, the base region being in contact with the source regions and the base contact regions. A junction between the source regions and the base region is closer to the drain portion side than a junction between the base contact regions and the base region.

    Field-effect transistor, semiconductor device, and photo relay
    7.
    发明申请
    Field-effect transistor, semiconductor device, and photo relay 失效
    场效应晶体管，半导体器件和照相继电器

    公开(公告)号：US20050230675A1

    公开(公告)日：2005-10-20

    申请号：US11001640

    申请日：2004-12-02

    申请人： Ryujiro Saso ,  Mitsuhiko Kitagawa ,  Takashi Nishimura ,  Yoshiaki Aizawa

    发明人： Ryujiro Saso ,  Mitsuhiko Kitagawa ,  Takashi Nishimura ,  Yoshiaki Aizawa

    IPC分类号： H01L31/12 ,  H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/1054 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/7835 ,  H01L29/7842 ,  H01L29/78624 ,  H01L29/78645

    摘要： According to the present invention, there is provided a field-effect transistor comprising: a silicon layer formed on an insulating film; a first-conductivity-type base layer formed in said silicon layer; a second-conductivity-type source layer formed in said silicon layer so as to be adjacent to said first-conductivity-type base layer; a second-conductivity-type drain layer formed in said silicon layer so as to be separated from said second-conductivity-type source layer with said first-conductivity-type base layer being interposed therebetween; a gate-to-drain offset layer formed between said first-conductivity-type base layer and said second-conductivity-type drain layer in said silicon layer, and having a resistance higher than that of said first-conductivity-type base layer; and a gate electrode formed on at least a surface of said first-conductivity-type base layer via a gate insulating film, wherein said silicon layer in which said first-conductivity-type base layer is formed is a strained silicon layer.

    摘要翻译： 根据本发明，提供了一种场效应晶体管，包括：在绝缘膜上形成的硅层; 形成在所述硅层中的第一导电型基底层; 形成在所述硅层中以与所述第一导电型基底层相邻的第二导电型源极层; 形成在所述硅层中的第二导电型漏极层，以与所述第二导电型源极层分离，所述第一导电型基极层插入其间; 在所述硅层中形成在所述第一导电型基极层和所述第二导电型漏极层之间并具有高于所述第一导电型基极层的电阻的栅极至漏极偏移层; 以及通过栅极绝缘膜形成在所述第一导电型基底层的至少表面上的栅电极，其中形成有所述第一导电型基底层的所述硅层是应变硅层。

    Insulated-gate semiconductor device
    9.
    发明授权
    Insulated-gate semiconductor device 失效
    绝缘栅半导体器件

    公开(公告)号：US5838026A

    公开(公告)日：1998-11-17

    申请号：US827530

    申请日：1997-03-28

    申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

    发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

    IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L21/36

    CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

    摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

    摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。